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1.发明授权公开(公告)号：US09503064B2
公开(公告)日：2016-11-22
申请号：US14792985
申请日：2015-07-07
Applicant: Samsung Electronics Co., Ltd.
Inventor： Gyeonghan Cha , Han-Kyul Lim , SungJun Kim , Chaeryung Kim , DongUk Park , Younwoong Chung , JungMyung Choi
Abstract: A skew calibration circuit may include a data delay unit receiving first data and a first code, and output delayed first data as second data by delaying the first data according to the first code; a clock delay unit receiving a first clock signal and a second code, and output delayed first clock signal as second clock signal by delaying the first clock signal according to the second code; a multiplexer receiving a clock signal and output the clock signal or an inverted clock signal of the clock signal as a first clock signal in response to a selection signal; and a control logic unit receiving the second data and the second clock signal and control the first code, the second code and the selection signal in response to the second data and the second clock signal.
Abstract translation: 偏斜校准电路可以包括接收第一数据和第一代码的数据延迟单元，并且通过根据第一代码延迟第一数据来将延迟的第一数据作为第二数据输出; 时钟延迟单元，接收第一时钟信号和第二代码，并且通过根据第二代码延迟第一时钟信号，将延迟的第一时钟信号作为第二时钟信号输出; 多路复用器响应于选择信号，接收时钟信号并输出时钟信号或时钟信号的反相时钟信号作为第一时钟信号; 以及控制逻辑单元，其接收第二数据和第二时钟信号，并且响应于第二数据和第二时钟信号来控制第一代码，第二代码和选择信号。
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公开(公告)号：US10943524B2
公开(公告)日：2021-03-09
申请号：US16427856
申请日：2019-05-31
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Dong-Chul Choi , Sung-Ho Kang , June-Hee Lee , Han-Kyul Lim , Byung-Wook Cho
Abstract: A device for generating restoration data by descrambling scramble data includes a linear feedback shift register configured to receive a first clock including a plurality of edges and sequentially generate a plurality of seeds including first to N−1th seeds (where N is a natural number of 2 or greater) respectively corresponding to first to N−1th edges among the plurality of edges, a seed calculator configured to calculate an Nth seed corresponding to an Nth edge among the plurality of edges by using the first seed, and a descrambler configured to descramble the scramble data by using the plurality of seeds generated by the linear feedback shift register and the Nth seed calculated by the seed calculator. The linear feedback shift register is further configured to generate an N+1th seed by using the Nth seed.
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公开(公告)号：US09071237B2
公开(公告)日：2015-06-30
申请号：US14207751
申请日：2014-03-13
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Cheon-Oh Lee , Tae-Pyeong Kim , Jung-Myung Choi , Sung-Jun Kim , Ho-Bin Song , Han-Kyul Lim
CPC classification number: H03K5/1565
Abstract: A digital duty cycle correction circuit includes a duty cycle controller and a digital duty control code generator. The duty cycle controller generates first and second output clock signals by compensating duty cycles of first and second input clock signals based on a digital duty control code. The digital duty control code generator generates the digital duty control code based on a frequency value obtained by converting duty cycle information of the first output clock signal and the second output clock signal.
Abstract translation: 数字占空比校正电路包括占空比控制器和数字占空比控制代码发生器。 占空比控制器通过基于数字占空比控制代码补偿第一和第二输入时钟信号的占空比来产生第一和第二输出时钟信号。 数字占空比控制码发生器基于通过转换第一输出时钟信号和第二输出时钟信号的占空比信息而获得的频率值来生成数字占空比控制码。
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公开(公告)号：US09059717B2
公开(公告)日：2015-06-16
申请号：US14147184
申请日：2014-01-03
Applicant: Samsung Electronics Co., Ltd.
Inventor： Tae-Pyeong Kim , Han-Kyul Lim , Dong-Uk Park
Abstract: A frequency compensation apparatus includes a first counter setting a reference period using a main clock, a second counter sensing a change in the frequency of a sub clock using the reference period, and a frequency compensator providing a compensated frequency using information on the changed frequency of the sub clock. Related methods are also described.
Abstract translation: 频率补偿装置包括使用主时钟设定基准周期的第一计数器，使用基准周期检测子时钟的频率变化的第二计数器和使用关于改变频率的信息的频率补偿器 子时钟。 还描述了相关方法。
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