公开(公告)号：US20230229073A1

公开(公告)日：2023-07-20

申请号：US18048205

申请日：2022-10-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Cheolhwan KIM ,  Jichang SIM ,  Jongmin LEE ,  Sangeun GO ,  Ohhun KWON ,  Hyuckjoon KWON

IPC: G03F1/36 ,  G03F1/70

CPC classification number: G03F1/36 ,  G03F1/70

Abstract: In a method of correcting a design layout of a semiconductor device, misaligned values of a portion of points of a target pattern of each of a plurality of regions of interest in a semiconductor device fabricated based on an original layout are measured, misaligned values of unmeasured points of the target pattern are estimated by using an artificial neural network trained based on the measured misaligned values of the portion of points, and a target layout of the semiconductor device is generated by using the estimated misaligned values.