公开(公告)号：US20150162335A1

公开(公告)日：2015-06-11

申请号：US14563269

申请日：2014-12-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dae-Ik KIM ,  Sung-Eui KIM ,  Hyoung-Sub KIM ,  Sung-Kwan CHOI

IPC: H01L27/105 ,  H01L21/311 ,  H01L21/02 ,  H01L49/02 ,  H01L21/768 ,  H01L21/306 ,  H01L23/522

CPC classification number: H01L21/768 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10852 ,  H01L27/10876 ,  H01L27/10885 ,  H01L28/91

Abstract: A method of manufacturing a semiconductor device includes forming an isolation layer on a substrate, where an active pattern is defined, forming an insulating interlayer on the active pattern of the substrate and the isolation layer, removing portions of the insulating interlayer, the active pattern and the isolation layer to form a first recess, forming a first contact in the first recess on a first region of the active pattern exposed by the first recess, removing portions of the active pattern and the isolation layer in the first recess by performing an isotropic etching process, to form an enlarged first recess, and filling the enlarged first recess to form a first spacer that surrounds a sidewall of the first contact.

Abstract translation: 一种制造半导体器件的方法包括在衬底上形成隔离层，其中限定有源图案，在衬底的有源图案和隔离层上形成绝缘中间层，去除绝缘层间的部分，活性图案和 所述隔离层形成第一凹部，在由所述第一凹部暴露的所述有源图案的第一区域上的所述第一凹部中形成第一接触，通过执行各向同性蚀刻来去除所述第一凹部中的所述有源图案的部分和所述隔离层 处理，以形成放大的第一凹部，并且填充放大的第一凹部以形成围绕第一接触件的侧壁的第一间隔件。

公开(公告)号：US20140145268A1

公开(公告)日：2014-05-29

申请号：US14017502

申请日：2013-09-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Je-Min PARK ,  Dae-Ik KIM

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L27/10894 ,  H01L21/76831 ,  H01L23/485 ,  H01L23/5222 ,  H01L27/10888 ,  H01L29/4236 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes an insulating interlayer over a substrate in a first region, the insulating layer including contact holes exposing a portion of a surface of the substrate, and contact plugs in the contact holes. The contact plugs include a stacked structure of a first barrier metal layer pattern and a first metal layer pattern. The semiconductor device also includes second metal layer patterns directly contacting with the contact plugs and an upper surface of the insulating interlayer. The second metal layer pattern consists is a metal material layer.

Abstract translation: 半导体器件包括在第一区域中的衬底上的绝缘中间层，所述绝缘层包括暴露衬底表面的一部分的接触孔以及接触孔中的接触插塞。 接触插塞包括第一阻挡金属层图案和第一金属层图案的堆叠结构。 半导体器件还包括与接触插塞直接接触的第二金属层图案和绝缘中间层的上表面。 第二金属层图案是金属材料层。

公开(公告)号：US20140154882A1

公开(公告)日：2014-06-05

申请号：US14097786

申请日：2013-12-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dae-Ik KIM ,  Ho-In RYU ,  Nak-Jin SON ,  Yoo-Sang HWANG

IPC: H01L27/108

CPC classification number: H01L27/10855 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10888

Abstract: A method for fabricating a semiconductor device includes forming a device isolation layer pattern on a substrate to form an active region, the active region including a first contact forming region at a center p of the active region and second and third contact forming regions at edges of the active region, forming an insulating layer and a first conductive layer on the substrate, forming a mask pattern having an isolated shape on the first conductive layer, etching the first conductive layer and the insulating layer to expose the active region of the first contact forming region by using the mask pattern, to form an opening portion between pillar structures, forming a second conductive layer in the opening, and patterning the second conductive layer and the first preliminary conductive layer pattern to form a wiring structure contacting the first contact forming region and having an extended line shape.

Abstract translation: 一种用于制造半导体器件的方法包括在衬底上形成器件隔离层图案以形成有源区，所述有源区包括位于有源区的中心p处的第一接触形成区和第二接触形成区 所述有源区，在所述基板上形成绝缘层和第一导电层，在所述第一导电层上形成具有隔离形状的掩模图案，蚀刻所述第一导电层和所述绝缘层，以暴露所述第一触点形成的有源区 通过使用掩模图案形成柱状结构之间的开口部分，在开口中形成第二导电层，图案化第二导电层和第一预导电层图案，以形成与第一接触形成区域接触的布线结构和 具有延长的线形。