公开(公告)号：US20210327476A1

公开(公告)日：2021-10-21

申请号：US17355765

申请日：2021-06-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DONGHUN LEE ,  Daesik MOON ,  Young-Soo SOHN ,  Young-Hoon SON ,  Ki-Seok OH ,  Changkyo LEE ,  Hyun-Yoon CHO ,  Kyung-Soo HA ,  Seokhun HYUN

IPC: G11C7/10 ,  G06F3/06

Abstract: A memory device includes a driver that drives a data line connected with an external device, an internal ZQ manager that generates an internal ZQ start signal, a selector that selects one of the internal ZQ start signal and a ZQ start command from the external device, based on a ZQ mode, a ZQ calibration engine that generates a ZQ code by performing ZQ calibration in response to a selection result of the selector, and a ZQ code register that loads the ZQ code onto the driver in response to a ZQ calibration command from the external device.

公开(公告)号：US20240347498A1

公开(公告)日：2024-10-17

申请号：US18409465

申请日：2024-01-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Daesik MOON ,  Sangwook PARK

IPC: H01L23/00 ,  H01L23/498 ,  H10B80/00

CPC classification number: H01L24/48 ,  H01L23/49827 ,  H01L24/49 ,  H10B80/00 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/32105 ,  H01L2224/32148 ,  H01L2224/48229 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2924/1436 ,  H01L2924/1438

Abstract: A memory device comprising: a semiconductor substrate; a plurality of wire bonding pads on the semiconductor substrate and arranged in a first direction; a plurality of signal redistribution patterns connecting first wire bonding pads among the plurality of wire bonding pads to a plurality of signal via pads, respectively, wherein the plurality of signal redistribution patterns are on a first side with respect to the plurality of wire bonding pads in a second direction that is perpendicular to the first direction; and a plurality of power redistribution patterns connected to second wire bonding pads among the plurality of wire bonding pads, respectively, wherein the plurality of power redistribution patterns are on a second side with respect to the plurality of wire bonding pads in the second direction, wherein the first and second directions are parallel with an upper surface of the semiconductor substrate.