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公开(公告)号：US12267086B2
公开(公告)日：2025-04-01
申请号：US18196244
申请日：2023-05-11
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Amit Berman , Dikla Shapiro , Idan Dekel
Abstract: Systems, devices, and methods for decoding information bits obtained from storage, including obtaining a frame corresponding to a codeword from the storage device, performing a first decoding operation on the frame, based on the first decoding operation indicating that a number of errors is greater than a predetermined number, selecting at least one potential error bit, and perform a second decoding operation based on the at least one potential error bit, based on the second decoding operation indicating that the number of errors is not equal to the predetermined number plus one, determining that the frame is not correctable by the first decoding operation and the second decoding operation, and based on the second decoding operation indicating that the number of errors is equal to the predetermined number plus one, correcting the frame based on a result of the second decoding operation to obtain a corrected frame, and obtaining information bits corresponding to the codeword based on the corrected frame.
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公开(公告)号：US20200228144A1
公开(公告)日：2020-07-16
申请号：US16244944
申请日：2019-01-10
Applicant: SAMSUNG ELECTRONICS CO., LTD
Inventor： ARIEL DOUBCHAK , Dikla Shapiro , Amit Berman
Abstract: A decoding circuit includes a Bose-Chaudhuri-Hocquenghem (BCH) decoder. The BCH decoder includes a Syndrome stage for generating syndromes based on a BCH encoded word, a Berlekamp-Massey (BM) stage performing a Berlekamp-Massey algorithm on the syndromes to generate Error Location Polynomial (ELP) coefficients, a Chien stage that performs a Chien search on the ELP coefficients using a Fast Fourier Transform (FFT) to generate error bits and iteration information, and a Frame Fixer stage configured to reorder the error bits to be sequential based on the iteration information. The BCH decoder decodes the BCH encoded word using the reordered error bits.
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公开(公告)号：US12199636B2
公开(公告)日：2025-01-14
申请号：US17983646
申请日：2022-11-09
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Dikla Shapiro , Amit Berman
Abstract: A method of operation for a Reed-Solomon decoder includes receiving partial input data of symbols of a Reed-Solomon codeword; updating Reed-Solomon syndromes and error location polynomial coefficients based on the partial input data; maintaining the Reed-Solomon syndromes and the error location polynomial coefficients in a memory prior to starting activation of Reed-Solomon decoding; and inputting the Reed-Solomon syndromes and the error location polynomial coefficients to a first activation of Reed-Solomon decoding including calculating an initial error evaluator polynomial as a first error evaluator polynomial, performing error detection based on the first error evaluator polynomial to determine presence and location of errors in an input Reed-Solomon codeword, and updating the error location polynomial when errors are found in the input Reed-Solomon codeword. The error location polynomial coefficients in the memory are updated during each activation of Reed-Solomon decoding when at least one error is identified in the Reed-Solomon codeword.
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Patent Agency Ranking
公开(公告)号：US12119840B2
公开(公告)日：2024-10-15
申请号：US18362137
申请日：2023-07-31
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Ariel Doubchak , Dikla Shapiro , Evgeny Blaichman , Lital Cohen , Amit Berman
CPC classification number: H03M13/1108 , G06N3/10 , H03M13/1111
Abstract: A machine-learning (ML) error-correcting code (ECC) controller may include a hard-decision (HD) ECC decoder optimized for high-speed data throughput, a soft-decision (SD) ECC decoder optimized for high-correctability data throughput, and a machine-learning equalizer (MLE) configured to variably select one of the HD ECC decoder or the SD ECC decoder for data throughput. An embodiment of the ML ECC controller may provide speed-optimized HD throughput based on a linear ECC. The linear ECC may be a soft Hamming permutation code (SHPC).
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公开(公告)号：US12224769B2
公开(公告)日：2025-02-11
申请号：US18196581
申请日：2023-05-12
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Amit Berman , Dikla Shapiro , Yaron Shany
Abstract: Systems, devices, and methods for decoding information bits obtained from storage, including obtaining a codeword from among a plurality of codewords stored in a storage device, wherein the codeword includes a plurality of frames; obtaining an initial error locator polynomial (ELP) corresponding to the codeword; decoding a frame of the plurality of frames; based on determining that the frame is successfully decoded, determine an updated ELP based on the initial ELP and information about the frame; and obtaining information bits corresponding to the codeword based on the updated ELP, wherein the updated ELP includes a plurality of updated coefficients, and wherein the updated ELP is determined by simultaneously calculating at least two updated coefficients from among the plurality of updated coefficients.
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公开(公告)号：US11742879B2
公开(公告)日：2023-08-29
申请号：US17495474
申请日：2021-10-06
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Ariel Doubchak , Dikla Shapiro , Evgeny Blaichman , Lital Cohen , Amit Berman
CPC classification number: H03M13/1108 , G06N3/10 , H03M13/1111
Abstract: A machine-learning (ML) error-correcting code (ECC) controller may include a hard-decision (HD) ECC decoder optimized for high-speed data throughput, a soft-decision (SD) ECC decoder optimized for high-correctability data throughput, and a machine-learning equalizer (MLE) configured to variably select one of the HD ECC decoder or the SD ECC decoder for data throughput. An embodiment of the ML ECC controller may provide speed-optimized HD throughput based on a linear ECC. The linear ECC may be a soft Hamming permutation code (SHPC).
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公开(公告)号：US11689216B1
公开(公告)日：2023-06-27
申请号：US17690124
申请日：2022-03-09
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Dikla Shapiro , Amit Berman , Ariel Doubchak
CPC classification number: H03M13/1108 , H03M13/152 , H03M13/1515 , H03M13/1575
Abstract: A device for decoding a generalized concatenated code (GCC) codeword includes: a buffer; and at least one processor configured to: obtain the GCC codeword, calculate a plurality of inner syndromes based on a plurality of frames; calculate a plurality of sets of delta syndromes based on the frames; determine a plurality of outer syndromes based on the sets of delta syndromes; store the inner syndromes and the outer syndromes in a buffer; perform inner decoding on the frames based on the inner syndromes stored in the buffer; update at least one outer syndrome stored in the buffer based on a result of the inner decoding; perform outer decoding on the frames based on the updated at least one outer syndrome; and obtain decoded information bits corresponding to the GCC codeword based on a result of the inner decoding and the result of the outer decoding.
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公开(公告)号：US11115055B2
公开(公告)日：2021-09-07
申请号：US16244944
申请日：2019-01-10
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Ariel Doubchak , Dikla Shapiro , Amit Berman
Abstract: A decoding circuit includes a Bose-Chaudhuri-Hocquenghem (BCH) decoder. The BCH decoder includes a Syndrome stage for generating syndromes based on a BCH encoded word, a Berlekamp-Massey (BM) stage performing a Berlekamp-Massey algorithm on the syndromes to generate Error Location Polynomial (ELP) coefficients, a Chien stage that performs a Chien search on the ELP coefficients using a Fast Fourier Transform (FFT) to generate error bits and iteration information, and a Frame Fixer stage configured to reorder the error bits to be sequential based on the iteration information. The BCH decoder decodes the BCH encoded word using the reordered error bits.
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