公开(公告)号：US20200111523A1

公开(公告)日：2020-04-09

申请号：US16388961

申请日：2019-04-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Keon LEE ,  Kyung-Soo Ha ,  Hyong-Ryol Hwang

IPC: G11C11/4076 ,  G11C11/408 ,  G11C11/4096 ,  H01L25/065 ,  H01L25/18 ,  G06F11/10 ,  G11C29/52

Abstract: A memory device is provided. The memory device receives a main clock signal and provides an internal main clock signal; a data clock buffer to receive a data clock signal; and a latency control circuit configured to generate latency information based on the data clock signal and provide the latency information to a data circuit. The latency control circuit includes: a divider configured to generate divided-by-two clock signals based on the data clock signal; a divider configured to generate divided-by-four clock signals based on a first group of the divided-by-two clock signals; a first synchronization detector configured to output divided-by-two alignment signals indicating whether a second group of divided-by-two clock signals is synchronized with the data clock signal; and a latency selector configured to detect phases of the divided-by-four clock signals based on the divided-by-two alignment signals and adjust a latency of the main clock signal based on the phases.