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    Semiconductor memory devices and methods of operating semiconductor memory devices
    1.
    发明授权
    Semiconductor memory devices and methods of operating semiconductor memory devices 有权

    公开(公告)号：US12148494B2

    公开(公告)日：2024-11-19

    申请号：US18115132

    申请日：2023-02-28

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kiheung Kim ,  Sanguhn Cha ,  Junhyung Kim ,  Sungchul Park ,  Hyojin Jung ,  Kyung-Soo Ha

    IPC: G11C29/42 ,  G11C11/406 ,  G11C29/20 ,  G11C29/44

    Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) circuit, a fault address register, a scrubbing control circuit and a control logic circuit. The memory cell array includes memory cell rows. The scrubbing control circuit generates scrubbing addresses based on refresh operations performed on the memory cell array. The control logic circuit controls the ECC circuit such that the ECC circuit performs an error detection operation on a plurality of sub-pages in a first memory cell row to count a number of error occurrences, and determines whether to correct a codeword in which an error is detected based on the number of error occurrences. An uncorrected or corrected codeword is written back, and a row address of the first memory cell row may be stored in the fault address register as a row fault address based on the number of error occurrences.

    BUFFER CIRCUIT FOR SEMICONDUCTOR DEVICE
    5.
    发明申请
    BUFFER CIRCUIT FOR SEMICONDUCTOR DEVICE 有权
    半导体器件的缓冲电路

    公开(公告)号：US20130214843A1

    公开(公告)日：2013-08-22

    申请号：US13717931

    申请日：2012-12-18

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kyung-Soo Ha ,  Ho-Seok Seol ,  Woo-Jin Lee

    IPC: H03K19/0185

    CPC classification number: H03K19/018514

    Abstract: A buffer circuit is provided which is insensitive to a duty distortion regardless of the change of operation environment. The buffer circuit includes a current mode logic buffer and a differential-to-single-ended converter. The differential-to-single-ended converter receives first and second differential output signals to generate a single ended output signal and is configured so that an internal control node of the differential-to-single-ended converter is controlled in a negative feedback method to maintain a constant duty ratio of the single ended output signal regardless of the change of operation environment. According to some embodiments, a duty distortion of the single ended output signal due to the change of operation environment such as a process, a voltage, a temperature, etc. is reduced or minimized and thereby performance of the buffer circuit is improved and operation reliability is improved.

    Abstract translation: 提供了缓冲电路，其对于占空比失真不敏感，而与操作环境的变化无关。 缓冲电路包括电流模式逻辑缓冲器和差分到单端转换器。 差分到单端转换器接收第一和第二差分输出信号以产生单端输出信号，并且被配置为使得差分到单端转换器的内部控制节点以负反馈方式被控制 保持单端输出信号的恒定占空比，而不管操作环境的变化。 根据一些实施例，减少或最小化由于诸如处理，电压，温度等的操作环境的改变引起的单端输出信号的占空比失真，从而提高缓冲电路的性能和操作可靠性 改进了

    Memory devices
    8.
    发明授权
    Memory devices 有权

    公开(公告)号：US10762947B2

    公开(公告)日：2020-09-01

    申请号：US16388961

    申请日：2019-04-19

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Dong-Keon Lee ,  Kyung-Soo Ha ,  Hyong-Ryol Hwang

    IPC: G11C11/4076 ,  G11C11/408 ,  G11C11/4096 ,  H01L25/065 ,  G06F11/10 ,  G11C29/52 ,  H01L25/18

    Abstract: A memory device is provided. The memory device receives a main clock signal and provides an internal main clock signal; a data clock buffer to receive a data clock signal; and a latency control circuit configured to generate latency information based on the data clock signal and provide the latency information to a data circuit. The latency control circuit includes: a divider configured to generate divided-by-two clock signals based on the data clock signal; a divider configured to generate divided-by-four clock signals based on a first group of the divided-by-two clock signals; a first synchronization detector configured to output divided-by-two alignment signals indicating whether a second group of divided-by-two clock signals is synchronized with the data clock signal; and a latency selector configured to detect phases of the divided-by-four clock signals based on the divided-by-two alignment signals and adjust a latency of the main clock signal based on the phases.

    MEMORY DEVICES
    9.
    发明申请
    MEMORY DEVICES 审中-公开

    公开(公告)号：US20200111523A1

    公开(公告)日：2020-04-09

    申请号：US16388961

    申请日：2019-04-19

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Dong-Keon LEE ,  Kyung-Soo Ha ,  Hyong-Ryol Hwang

    IPC: G11C11/4076 ,  G11C11/408 ,  G11C11/4096 ,  H01L25/065 ,  H01L25/18 ,  G06F11/10 ,  G11C29/52

    Abstract: A memory device is provided. The memory device receives a main clock signal and provides an internal main clock signal; a data clock buffer to receive a data clock signal; and a latency control circuit configured to generate latency information based on the data clock signal and provide the latency information to a data circuit. The latency control circuit includes: a divider configured to generate divided-by-two clock signals based on the data clock signal; a divider configured to generate divided-by-four clock signals based on a first group of the divided-by-two clock signals; a first synchronization detector configured to output divided-by-two alignment signals indicating whether a second group of divided-by-two clock signals is synchronized with the data clock signal; and a latency selector configured to detect phases of the divided-by-four clock signals based on the divided-by-two alignment signals and adjust a latency of the main clock signal based on the phases.

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