公开(公告)号：US11728345B2

公开(公告)日：2023-08-15

申请号：US17345090

申请日：2021-06-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-chan Suh ,  Gi-gwan Park ,  Dong-woo Kim ,  Dong-suk Shin

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/165 ,  H01L29/66 ,  H01L29/04 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L27/0924 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/092 ,  H01L29/045 ,  H01L29/0665 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/6656 ,  H01L29/66545 ,  H01L29/78696

Abstract: A semiconductor device includes a substrate including a first region and a second region, fin type active areas extending in a first direction away from the substrate in each of the first and second regions, a plurality of nanosheets extending parallel to an upper surface of the fin type active areas and being spaced apart from the upper surface of the fin type active areas, a gate extending over the fin type active areas in a second direction crossing the first direction, a gate dielectric layer interposed between the gate and each of the nanosheets, first source and drain regions included in the first region and second source and drain regions included in the second region, and insulating spacers interposed between the fin type active areas and the nanosheets, wherein air spacers are interposed between the insulating spacers and the first source and drain regions.

公开(公告)号：US20190259840A1

公开(公告)日：2019-08-22

申请号：US16392000

申请日：2019-04-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-woo Kim ,  Hyun-ho Noh ,  Yong-seung Kim ,  Dong-suk Shin ,  Kwan-heum Lee ,  Yu-yeong Jo

IPC: H01L29/161 ,  H01L29/167 ,  H01L29/08 ,  H01L29/78 ,  H01L29/04

Abstract: Provided is a semiconductor device including: a fin structure on a substrate including a negative channel field-effect transistor (nFET) region and a positive channel field-effect transistor (pFET) region; a gate structure on the fin structure; and a source/drain structure adjacent to the gate structure, wherein the source/drain structure formed in the nFET region is an epitaxial layer including an n-type impurity at a concentration of about 1.8×1021/cm3 or more, includes silicon (Si) and germanium (Ge) on an outer portion of the source/drain structure, and includes Si but not Ge in an inner portion of the source/drain structure, wherein an inclined surface contacting an uppermost surface of the source/drain structure forms an angle of less than about 54.7° with a top surface of the fin structure.

公开(公告)号：US10361202B2

公开(公告)日：2019-07-23

申请号：US15611893

申请日：2017-06-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-chan Suh ,  Gi-gwan Park ,  Dong-woo Kim ,  Dong-suk Shin

IPC: H01L29/66 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/165 ,  H01L29/04 ,  H01L29/06

Abstract: A semiconductor device includes a substrate including a first region and a second region, fin type active areas extending in a first direction away from the substrate in each of the first and second regions, a plurality of nanosheets extending parallel to an upper surface of the fin type active areas and being spaced apart from the upper surface of the fin type active areas, a gate extending over the fin type active areas in a second direction crossing the first direction, a gate dielectric layer interposed between the gate and each of the nanosheets, first source and drain regions included in the first region and second source and drain regions included in the second region, and insulating spacers interposed between the fin type active areas and the nanosheets, wherein air spacers are interposed between the insulating spacers and the first source and drain regions.

公开(公告)号：US20190006469A1

公开(公告)日：2019-01-03

申请号：US15871374

申请日：2018-01-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-woo Kim ,  Hyun-ho Noh ,  Yong-seung Kim ,  Dong-suk Shin ,  Kwan-heum Lee ,  Yu-yeong Jo

IPC: H01L29/161 ,  H01L29/08 ,  H01L29/167 ,  H01L29/04 ,  H01L29/78

Abstract: Provided is a semiconductor device including: a fin structure on a substrate including a negative channel field-effect transistor (nFET) region and a positive channel field-effect transistor (pFET) region; a gate structure on the fin structure; and a source/drain structure adjacent to the gate structure, wherein the source/drain structure formed in the nFET region is an epitaxial layer including an n-type impurity at a concentration of about 1.8×1021/cm3 or more, includes silicon (Si) and germanium (Ge) on an outer portion of the source/drain structure, and includes Si but not Ge in an inner portion of the source/drain structure, wherein an inclined surface contacting an uppermost surface of the source/drain structure forms an angle of less than about 54.7° with a top surface of the fin structure.

公开(公告)号：US12225741B2

公开(公告)日：2025-02-11

申请号：US18216041

申请日：2023-06-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-chan Suh ,  Gi-gwan Park ,  Dong-woo Kim ,  Dong-suk Shin

IPC: H01L27/092

Abstract: A semiconductor device includes a substrate including a first region and a second region, fin type active areas extending in a first direction away from the substrate in each of the first and second regions, a plurality of nanosheets extending parallel to an upper surface of the fin type active areas and being spaced apart from the upper surface of the fin type active areas, a gate extending over the fin type active areas in a second direction crossing the first direction, a gate dielectric layer interposed between the gate and each of the nanosheets, first source and drain regions included in the first region and second source and drain regions included in the second region, and insulating spacers interposed between the fin type active areas and the nanosheets, wherein air spacers are interposed between the insulating spacers and the first source and drain regions.

公开(公告)号：US11037926B2

公开(公告)日：2021-06-15

申请号：US17014254

申请日：2020-09-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-chan Suh ,  Gi-gwan Park ,  Dong-woo Kim ,  Dong-suk Shin

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/165 ,  H01L29/66 ,  H01L29/04 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

Abstract: A semiconductor device includes a substrate including a first region and a second region, fin type active areas extending in a first direction away from the substrate in each of the first and second regions, a plurality of nanosheets extending parallel to an upper surface of the fin type active areas and being spaced apart from the upper surface of the fin type active areas, a gate extending over the fin type active areas in a second direction crossing the first direction, a gate dielectric layer interposed between the gate and each of the nanosheets, first source and drain regions included in the first region and second source and drain regions included in the second region, and insulating spacers interposed between the fin type active areas and the nanosheets, wherein air spacers are interposed between the insulating spacers and the first source and drain regions.

公开(公告)号：US10790361B2

公开(公告)日：2020-09-29

申请号：US16392000

申请日：2019-04-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-woo Kim ,  Hyun-ho Noh ,  Yong-seung Kim ,  Dong-suk Shin ,  Kwan-heum Lee ,  Yu-yeong Jo

IPC: H01L29/161 ,  H01L29/08 ,  H01L29/78 ,  H01L29/04 ,  H01L29/167

Abstract: Provided is a semiconductor device including: a fin structure on a substrate including a negative channel field-effect transistor (nFET) region and a positive channel field-effect transistor (pFET) region; a gate structure on the fin structure; and a source/drain structure adjacent to the gate structure, wherein the source/drain structure formed in the nFET region is an epitaxial layer including an n-type impurity at a concentration of about 1.8×1021/cm3 or more, includes silicon (Si) and germanium (Ge) on an outer portion of the source/drain structure, and includes Si but not Ge in an inner portion of the source/drain structure, wherein an inclined surface contacting an uppermost surface of the source/drain structure forms an angle of less than about 54.7° with a top surface of the fin structure.

公开(公告)号：US10304932B2

公开(公告)日：2019-05-28

申请号：US15871374

申请日：2018-01-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-woo Kim ,  Hyun-ho Noh ,  Yong-seung Kim ,  Dong-suk Shin ,  Kwan-heum Lee ,  Yu-yeong Jo

IPC: H01L29/80 ,  H01L21/00 ,  H01L29/161 ,  H01L29/08 ,  H01L29/78 ,  H01L29/04 ,  H01L29/167

Abstract: Provided is a semiconductor device including: a fin structure on a substrate including a negative channel field-effect transistor (nFET) region and a positive channel field-effect transistor (pFET) region; a gate structure on the fin structure; and a source/drain structure adjacent to the gate structure, wherein the source/drain structure formed in the nFET region is an epitaxial layer including an n-type impurity at a concentration of about 1.8×1021/cm3 or more, includes silicon (Si) and germanium (Ge) on an outer portion of the source/drain structure, and includes Si but not Ge in an inner portion of the source/drain structure, wherein an inclined surface contacting an uppermost surface of the source/drain structure forms an angle of less than about 54.7° with a top surface of the fin structure.