公开(公告)号：US12237183B2

公开(公告)日：2025-02-25

申请号：US17210686

申请日：2021-03-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyoungsik Cho ,  Hogon Kim ,  Myoungryul Han ,  Hyunchul Kwun ,  Dongha Kim ,  Jangho Son

IPC: H01L21/67 ,  C23C16/458 ,  C23C16/46 ,  C23C16/52 ,  H01J37/32

Abstract: A semiconductor processing system includes; a chamber, a substrate support disposed in the chamber, and a temperature controller including a thermal section disposed under the substrate support and a coupling section including at least one coupling section member. The thermal section includes a first plate and a second plate spaced apart under the substrate support, and each of the first plate and the second plate is coupled to a side portion of the substrate by at least one coupling section member.

公开(公告)号：US20240038288A1

公开(公告)日：2024-02-01

申请号：US18171121

申请日：2023-02-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongha Kim ,  Hyunki Kim ,  Sungchul Park ,  Ju-Seop Park ,  Dongsu Lee

IPC: G11C11/406

CPC classification number: G11C11/40622 ,  G11C11/40611 ,  G11C11/40603

Abstract: In a memory device, a control circuit detects determines an aggressor row address, indicating an aggressor row of a memory cell array, at a random time. The aggressor row address or a value derived from the aggressor row address is stored in a queue. The control circuit controls a refresh operation of one or more victim rows based on the aggressor row address in response to a targeted refresh command.

公开(公告)号：US20240339145A1

公开(公告)日：2024-10-10

申请号：US18422770

申请日：2024-01-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongha Kim ,  Tae-Kyeong Ko ,  Do-Han Kim

IPC: G11C11/406 ,  G11C11/4078

CPC classification number: G11C11/40615 ,  G11C11/40622 ,  G11C11/4078

Abstract: The present disclosure relates to operation methods of a memory device including multiple rows each including multiple memory cells. One example method includes receiving an active command for a first row from a memory controller, reading a first count from a per-row hammer tracking (PRHT) region of the first row, updating the first count to generate a first updated count, comparing the first updated count with one of first and second thresholds to generate a comparison result, wherein when the first row is adjacent to the given row, the first updated count is compared with the first threshold and when the first row is not adjacent to the given row, the first updated count is compared with the second threshold, outputting a target row address based on the comparison result, and performing a row hammer mitigation operation on a row corresponding to the target row address.

公开(公告)号：US11615829B1

公开(公告)日：2023-03-28

申请号：US17244261

申请日：2021-04-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongha Kim ,  Hyunki Kim ,  Hoyoung Song

IPC: G11C11/406 ,  G11C11/408

Abstract: A memory device includes a memory cell array, a random bit generator, a comparator and a refresh controller. The memory cell array includes a plurality of memory cells coupled to a plurality of word-lines. The random bit generator generates a random binary code having a predetermined number of bits. The comparator compares the random binary code and a reference binary code to output a matching signal based on a result of the comparison. The refresh controller refreshes target memory cells from among the plurality of memory cells based on addresses accessed by a memory controller during a sampling period randomly determined based on the matching signal and a refresh command from the memory controller.