SEMICONDUCTOR PACKAGE HAVING A CONTROLLER

    公开(公告)号:US20250118689A1

    公开(公告)日:2025-04-10

    申请号:US18782386

    申请日:2024-07-24

    Abstract: A semiconductor package includes a substrate having first and second sides, pads disposed on the substrate and including first and second bonding pads adjacent to the first and second sides, respectively, and upper pads between the first and second bonding pads, a passivation layer disposed on the substrate and exposing the first and second bonding pads, a solder resist layer disposed on the passivation layer, a first chip structure on the solder resist layer, adjacent to the first side and electrically connected to the first bonding pads, a second chip structure on the solder resist layer, adjacent to the second side and electrically connected to the second bonding pads, a controller on the solder resist layer between the first and the second chip structure, and a connection structure penetrating the passivation layer and the solder resist layer and electrically connecting the controller and the upper pads.

    Memory device performing refresh operation based on a random value and method of operating the same

    公开(公告)号:US11615829B1

    公开(公告)日:2023-03-28

    申请号:US17244261

    申请日:2021-04-29

    Abstract: A memory device includes a memory cell array, a random bit generator, a comparator and a refresh controller. The memory cell array includes a plurality of memory cells coupled to a plurality of word-lines. The random bit generator generates a random binary code having a predetermined number of bits. The comparator compares the random binary code and a reference binary code to output a matching signal based on a result of the comparison. The refresh controller refreshes target memory cells from among the plurality of memory cells based on addresses accessed by a memory controller during a sampling period randomly determined based on the matching signal and a refresh command from the memory controller.

    SEMICONDUCTOR PACKAGE
    3.
    发明申请

    公开(公告)号:US20200350288A1

    公开(公告)日:2020-11-05

    申请号:US16680657

    申请日:2019-11-12

    Abstract: A semiconductor package including a circuit substrate including a plurality of interconnections; a first chip on the circuit substrate; a second chip stacked on the first chip; a plurality of first pads on the circuit substrate, the plurality of first pads overlapping the first chip; a plurality of bumps between the circuit substrate and the first chip; a plurality of second pads on an edge portion of a first side of the circuit substrate, the plurality of second pads electrically connected to the second chip through a conductive wire; an underfill that fills a space between the circuit substrate and the first chip; and a first dam on the circuit substrate, the first dam overlapping the first chip. The first dam includes a conductive material and overlaps at least one of the plurality of interconnections.

    SEMICONDUCTOR PACKAGE
    7.
    发明申请

    公开(公告)号:US20220392846A1

    公开(公告)日:2022-12-08

    申请号:US17887557

    申请日:2022-08-15

    Abstract: A semiconductor package includes a first substrate, a second substrate provided on the first substrate, a semiconductor chip provided between the first substrate and the second substrate, solder structures extending between the first substrate and the second substrate and spaced apart from the semiconductor chip, and bumps provided between the semiconductor chip and the second substrate. The solder structures electrically connect the first substrate and the second substrate.

    MEMORY DEVICES HAVING VARIABLE REPAIR UNITS THEREIN AND METHODS OF REPAIRING SAME

    公开(公告)号:US20210124659A1

    公开(公告)日:2021-04-29

    申请号:US16890559

    申请日:2020-06-02

    Abstract: A memory device includes a row decoder, a column decoder, and a repair control circuit, which is configured to: (i) compare a row address with a stored failed row address, (ii) compare a column address with a stored failed column address, (iii) control the row decoder to activate the at least one of a plurality of redundancy word lines when the row address corresponds to the failed row address, and (iv) control the column decoder to activate at least one of a plurality of redundancy bit lines when the column address corresponds to the failed column address. The repair control circuit varies a repair unit according to an address input during a repair operation.

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