公开(公告)号：US20230200072A1

公开(公告)日：2023-06-22

申请号：US17876877

申请日：2022-07-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Younghwan SON ,  Dongkeun LEE

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573

CPC classification number: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573

Abstract: Provided is a method including forming a mold structure including insulating layers and sacrificial layers alternately stacked on a semiconductor substrate, the insulating layers exposing stepwise-stacked ends of the sacrificial layers on a connection region of the semiconductor substrate, forming a sacrificial oxide layer to cover the exposed ends , forming sacrificial pad patterns on the exposed ends, respectively, forming a planarization insulating layer to cover the sacrificial oxide layer and the sacrificial pad patterns, forming a vertical contact hole to penetrate the planarization insulating layer, each of the sacrificial pad patterns, the sacrificial oxide layer and the mold structure, removing each of the sacrificial pad patterns to form a recess region, removing a portion of the sacrificial oxide layer exposed by the recess region to form an extended recess region, and forming a cell contact plug to fill the vertical contact hole and the extended recess region.