公开(公告)号：US20200013595A1

公开(公告)日：2020-01-09

申请号：US16259185

申请日：2019-01-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yongwoo LEE ,  Youngjin NOH ,  Dowon KIM ,  Donghyeon NA ,  Seungbo SHIM

IPC: H01J37/32 ,  H01L21/67 ,  H01L21/683

Abstract: An electrostatic chuck includes a chuck base having a first hole, an upper plate provided on the chuck base, the upper plate having a second hole aligned with the first hole, and an adhesive layer attaching the upper plate to the chuck base, the adhesive layer having a thickness that is less than a diameter of the first hole and equal to a diameter of the second hole.

公开(公告)号：US20240124972A1

公开(公告)日：2024-04-18

申请号：US18133909

申请日：2023-04-12

Applicant: SAMSUNG ELECTRONICS Co., LTD.

Inventor： Kyungrim KIM ,  Dowon KIM ,  Sunja KIM ,  Youngeun KIM

IPC: C23C16/448 ,  C23C16/455 ,  C23C16/52

CPC classification number: C23C16/4481 ,  C23C16/45527 ,  C23C16/45544 ,  C23C16/45553 ,  C23C16/52

Abstract: A canister supplying a precursor to a processing chamber includes a body, a first valve introducing a carrier gas into the body, a second valve discharging a sublimated gas of a solid precursor into a processing chamber, a precursor accommodating tray accommodating the solid precursor, and at least one piezoelectric transducer at least one of vibrating the precursor accommodating tray or measuring a resonance frequency.

公开(公告)号：US20230057039A1

公开(公告)日：2023-02-23

申请号：US17722689

申请日：2022-04-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myeongho HONG ,  Dowon KIM ,  Jangbae SON ,  Seokwoo YOON ,  Kyomuk LIM

IPC: H01L23/538 ,  H01L23/498 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48 ,  H01L23/00

Abstract: A package structure includes a core substrate including a substrate base including a plurality of first cavities and a plurality of second cavities, a plurality of blocks in the plurality of second cavities; and a plurality of bridge structures that extend between each of the plurality of blocks and the substrate base, a plurality of semiconductor chips in the plurality of first cavities, and a molding layer configured to cover the core substrate and the plurality of semiconductor chips, a portion of the molding layer being in the plurality of first cavities and the plurality of second cavities.