公开(公告)号：US20240250011A1

公开(公告)日：2024-07-25

申请号：US18351975

申请日：2023-07-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myeongho HONG ,  Hyunseok CHOI

IPC: H01L23/498 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/538 ,  H01L25/00 ,  H01L25/10

CPC classification number: H01L23/49838 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/5383 ,  H01L23/5389 ,  H01L24/08 ,  H01L24/16 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/08225 ,  H01L2224/16227

Abstract: The present disclosure relates to fan-out semiconductor packages and a methods for manufacturing the same. A fan-out semiconductor package includes a substrate including a cavity, a semiconductor die within the cavity and including a plurality of connection terminals at a bottom surface thereof, a dummy die at a fan-out region within the cavity and including a plurality of through silicon vias (TSVs), a filler filling an empty space within the cavity, and a lower redistribution layer on bottom surfaces of the substrate, the semiconductor die, and the dummy die, and electrically connected to at least some of the plurality of connection terminals of the semiconductor die and the plurality of through silicon vias of the dummy die, and an upper redistribution layer on top surfaces of the substrate, the semiconductor die, and the dummy die, and electrically connected to the plurality of through silicon vias of the dummy die.

公开(公告)号：US20230057039A1

公开(公告)日：2023-02-23

申请号：US17722689

申请日：2022-04-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myeongho HONG ,  Dowon KIM ,  Jangbae SON ,  Seokwoo YOON ,  Kyomuk LIM

IPC: H01L23/538 ,  H01L23/498 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48 ,  H01L23/00

Abstract: A package structure includes a core substrate including a substrate base including a plurality of first cavities and a plurality of second cavities, a plurality of blocks in the plurality of second cavities; and a plurality of bridge structures that extend between each of the plurality of blocks and the substrate base, a plurality of semiconductor chips in the plurality of first cavities, and a molding layer configured to cover the core substrate and the plurality of semiconductor chips, a portion of the molding layer being in the plurality of first cavities and the plurality of second cavities.