公开(公告)号：US20210257264A1

公开(公告)日：2021-08-19

申请号：US17246778

申请日：2021-05-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SANGMIN YOO ,  JUYOUN KIM ,  HYUNGJOO NA ,  BONGSEOK SUH ,  JOOHO JUNG ,  EUICHUL HWANG ,  SUNGMOON LEE

IPC: H01L21/8238 ,  H01L27/118 ,  H01L21/762

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate including an active pattern, a gate electrode extending in a first direction and crossing the active pattern which extends in a second direction, a separation structure crossing the active pattern and extending in the first direction, a first gate dielectric pattern disposed on a side surface of the gate electrode, a second gate dielectric pattern disposed on a side surface of the separation structure, and a gate capping pattern covering a top surface of the gate electrode. A level of a top surface of the separation structure is higher than a level of a top surface of the gate capping pattern.

公开(公告)号：US20230253264A1

公开(公告)日：2023-08-10

申请号：US18300983

申请日：2023-04-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SANGMIN YOO ,  JUYOUN KIM ,  HYUNGJOO NA ,  BONGSEOK SUH ,  JOOHO JUNG ,  EUICHUL HWANG ,  SUNGMOON LEE

IPC: H01L21/8238 ,  H01L27/118 ,  H01L21/762

CPC classification number: H01L21/823878 ,  H01L27/11807 ,  H01L21/76224 ,  H01L2027/11861 ,  H01L2027/11829 ,  H01L2027/11816

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate including an active pattern, a gate electrode extending in a first direction and crossing the active pattern which extends in a second direction, a separation structure crossing the active pattern and extending in the first direction, a first gate dielectric pattern disposed on a side surface of the gate electrode, a second gate dielectric pattern disposed on a side surface of the separation structure, and a gate capping pattern covering a top surface of the gate electrode. A level of a top surface of the separation structure is higher than a level of a top surface of the gate capping pattern.