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公开(公告)号：US11824059B2
公开(公告)日：2023-11-21
申请号：US17369236
申请日：2021-07-07
发明人： Keun Hwi Cho , Sangdeok Kwon , Dae Sin Kim , Dongwon Kim , Yonghee Park , Hagju Cho
IPC分类号： H01L27/118 , H01L21/8238 , H01L27/02 , H01L27/092
CPC分类号： H01L27/11807 , H01L21/82385 , H01L21/823821 , H01L21/823871 , H01L27/0207 , H01L27/0924 , H01L2027/11829 , H01L2027/11851 , H01L2027/11861 , H01L2027/11881 , H01L2027/11885
摘要： A semiconductor device includes first and second active patterns respectively on the first and second active regions of a substrate, a gate electrode on the first and second channel patterns, active contacts electrically connected to at least one of the first and second source/drain patterns, a gate contact electrically connected to the gate electrode, a first metal layer on the active and gate contacts and including a first and second power line, and first and second gate cutting patterns below the first and second power lines. The first active pattern may include first channel pattern between a pair of first source/drain patterns. The second active pattern may include a second channel pattern between a pair of second source/drain patterns. The first and second gate cutting patterns may cover the outermost side surfaces of the first and second channel patterns, respectively.
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公开(公告)号：US20230253264A1
公开(公告)日：2023-08-10
申请号：US18300983
申请日：2023-04-14
发明人： SANGMIN YOO , JUYOUN KIM , HYUNGJOO NA , BONGSEOK SUH , JOOHO JUNG , EUICHUL HWANG , SUNGMOON LEE
IPC分类号： H01L21/8238 , H01L27/118 , H01L21/762
CPC分类号： H01L21/823878 , H01L27/11807 , H01L21/76224 , H01L2027/11861 , H01L2027/11829 , H01L2027/11816
摘要： A semiconductor device is provided. The semiconductor device includes a substrate including an active pattern, a gate electrode extending in a first direction and crossing the active pattern which extends in a second direction, a separation structure crossing the active pattern and extending in the first direction, a first gate dielectric pattern disposed on a side surface of the gate electrode, a second gate dielectric pattern disposed on a side surface of the separation structure, and a gate capping pattern covering a top surface of the gate electrode. A level of a top surface of the separation structure is higher than a level of a top surface of the gate capping pattern.
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公开(公告)号：US11658075B2
公开(公告)日：2023-05-23
申请号：US17246778
申请日：2021-05-03
发明人： Sangmin Yoo , Juyoun Kim , Hyungjoo Na , Bongseok Suh , Jooho Jung , Euichul Hwang , Sungmoon Lee
IPC分类号： H01L27/088 , H01L21/8234 , H01L23/522 , H01L29/06 , H01L21/311 , H01L21/8238 , H01L27/118 , H01L21/762
CPC分类号： H01L21/823878 , H01L21/76224 , H01L27/11807 , H01L2027/11816 , H01L2027/11829 , H01L2027/11861
摘要： A semiconductor device is provided. The semiconductor device includes a substrate including an active pattern, a gate electrode extending in a first direction and crossing the active pattern which extends in a second direction, a separation structure crossing the active pattern and extending in the first direction, a first gate dielectric pattern disposed on a side surface of the gate electrode, a second gate dielectric pattern disposed on a side surface of the separation structure, and a gate capping pattern covering a top surface of the gate electrode. A level of a top surface of the separation structure is higher than a level of a top surface of the gate capping pattern.
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公开(公告)号：US20180366463A1
公开(公告)日：2018-12-20
申请号：US15926572
申请日：2018-03-20
发明人： Moon Gi Cho , Hyeonuk Kim , Jongchan Shin , Eryung Hwang , Jaeseok Yang , Jinwoo Jeong
IPC分类号： H01L27/088 , H01L29/06 , H01L23/528
CPC分类号： H01L27/088 , H01L21/823475 , H01L21/823481 , H01L23/5226 , H01L23/528 , H01L23/53233 , H01L23/53295 , H01L27/0207 , H01L27/092 , H01L27/11504 , H01L27/11519 , H01L27/11565 , H01L27/11587 , H01L27/11807 , H01L29/0646 , H01L29/785 , H01L2027/11829 , H01L2027/11875
摘要： Semiconductor devices are provided. A semiconductor device includes a gate structure and an adjacent contact. The semiconductor device includes a connector that is connected to the contact. In some embodiments, the semiconductor device includes a wiring pattern that is connected to the connector. Moreover, in some embodiments, the connector is adjacent a boundary between first and second cells of the semiconductor device.
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公开(公告)号：US11705456B2
公开(公告)日：2023-07-18
申请号：US17200179
申请日：2021-03-12
发明人： Sanghoon Baek , Jungho Do , Jaewoo Seo , Jisu Yu
IPC分类号： H01L27/118 , H01L27/02 , H01L23/48
CPC分类号： H01L27/11807 , H01L23/481 , H01L27/0207 , H01L2027/11829 , H01L2027/11864 , H01L2027/11881
摘要： A semiconductor device includes a first standard cell disposed on a substrate in a first row and having a first cell height; a second standard cell disposed on the substrate in a second row, adjacent to the first row, second standard cell having a second cell height, different from the first cell height; and a power line extending in a first direction along a boundary between the first standard cell and the second standard cell.
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公开(公告)号：US20230215868A1
公开(公告)日：2023-07-06
申请号：US18176463
申请日：2023-02-28
发明人： YOUNG-HUN KIM , JAE-SEOK YANG , HAE-WANG LEE
IPC分类号： H01L27/118 , H01L21/8238 , H01L27/02
CPC分类号： H01L27/11807 , H01L21/823814 , H01L27/0207 , H01L21/823878 , H01L2027/11864 , H01L2027/11861 , H01L2027/11829 , H01L2027/11881
摘要： A semiconductor device includes a substrate having cell areas and power areas that are alternately arranged in a second direction. Gate structures extend in the second direction. The gate structures are spaced apart from each other in a first direction perpendicular to the second direction. Junction layers are arranged at both sides of each gate structure. The junction layers are arranged in the second direction such that each of the junction layer has a flat portion that is proximate to the power area. Cutting patterns are arranged in the power areas. The cutting patterns extend in the first direction such that each of the gate structures and each of the junction layers in neighboring cell areas are separated from each other by the cutting pattern.
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公开(公告)号：US09947661B2
公开(公告)日：2018-04-17
申请号：US15641417
申请日：2017-07-05
发明人： Raheel Azmat , Sharma Deepak , Chulhong Park
IPC分类号： H01L27/02 , H01L27/088 , H01L21/8238 , H01L23/522 , H01L29/08 , H01L29/06 , H01L23/528 , H01L27/118 , H01L21/8234 , H01L27/092
CPC分类号： H01L27/0886 , H01L21/823431 , H01L21/823821 , H01L23/5226 , H01L23/528 , H01L27/0207 , H01L27/088 , H01L27/0924 , H01L27/11807 , H01L29/0649 , H01L29/0847 , H01L2027/11829 , H01L2027/11875
摘要： A semiconductor device, and a method of manufacturing the same, includes first and second gate structures extending in a first direction and spaced apart from each other in a second direction intersecting the first direction, a dummy gate structure provided between the first and second gate structures, a first source/drain region between the first gate structure and the dummy gate structure, a second source/drain region between the second gate structure and the dummy gate structure, a connection contact provided on the dummy gate structure, and a common conductive line provided on the connection contact. The dummy gate structure extends in the first direction. The connection contact extends in the second direction to connect the first source/drain region to the second source/drain region. The common conductive line configured to a voltage to the first and second source/drain regions through the connection contact.
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公开(公告)号：US20180053783A1
公开(公告)日：2018-02-22
申请号：US15796329
申请日：2017-10-27
申请人： Socionext Inc.
发明人： Masaki TAMARU
IPC分类号： H01L27/118 , H01L23/485 , H01L27/02 , H01L29/10 , H01L21/768
CPC分类号： H01L27/11807 , H01L21/76895 , H01L23/485 , H01L27/0207 , H01L29/1079 , H01L2027/11829 , H01L2027/11861 , H01L2027/11866 , H01L2027/11875 , H01L2924/0002 , H01L2924/00
摘要： A local interconnect is formed in contact with an upper surface of an impurity diffusion region and extends to below a potential supply interconnect. A contact hole electrically couples the local interconnect to the potential supply interconnect. The local interconnect, which is formed in contact with the upper surface of the impurity diffusion region, is used for electrically coupling the impurity diffusion region to the potential supply interconnect.
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公开(公告)号：US20160322355A1
公开(公告)日：2016-11-03
申请号：US15206610
申请日：2016-07-11
发明人： Raheel AZMAT , Sharma DEEPAK , Chulhong PARK
IPC分类号： H01L27/088 , H01L23/522 , H01L29/08 , H01L27/02 , H01L23/528 , H01L29/06
CPC分类号： H01L27/0886 , H01L21/823431 , H01L21/823821 , H01L23/5226 , H01L23/528 , H01L27/0207 , H01L27/088 , H01L27/0924 , H01L27/11807 , H01L29/0649 , H01L29/0847 , H01L2027/11829 , H01L2027/11875
摘要： A semiconductor device, and a method of manufacturing the same, includes first and second gate structures extending in a first direction and spaced apart from each other in a second direction intersecting the first direction, a dummy gate structure provided between the first and second gate structures, a first source/drain region between the first gate structure and the dummy gate structure, a second source/drain region between the second gate structure and the dummy gate structure, a connection contact provided on the dummy gate structure, and a common conductive line provided on the connection contact. The dummy gate structure extends in the first direction. The connection contact extends in the second direction to connect the first source/drain region to the second source/drain region. The common conductive line configured to a voltage to the first and second source/drain regions through the connection contact.
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公开(公告)号：US20180102364A1
公开(公告)日：2018-04-12
申请号：US15603577
申请日：2017-05-24
发明人： Sidharth RASTOGI , Subhash KUCHANURI , Raheel AZMAT , Pan-jae PARK , Chul-hong PARK , Jae-seok YANG , Kwan-young CHUN
IPC分类号： H01L27/092 , H01L29/49 , H01L29/06 , H01L23/535
CPC分类号： H01L27/092 , H01L21/76 , H01L21/76895 , H01L21/823828 , H01L21/823871 , H01L23/535 , H01L27/0207 , H01L27/0924 , H01L29/0649 , H01L29/41791 , H01L29/4966 , H01L29/785 , H01L2027/11829
摘要： An integrated circuit device includes a substrate including a fin active region extending in a first direction, a gate line intersecting the fin active region and extending in a second direction perpendicular to the first direction, a power line electrically connected to source/drain regions at sides of the gate line on the fin active region, a pair of dummy gate lines intersecting the fin active region and extending in the second direction, and a device separation structure electrically connected to the pair of dummy gate lines and including a lower dummy contact plug between the pair of dummy gate lines on the fin active region and electrically connected to the power line, and an upper dummy contact plug on the lower dummy contact plug and on the pair of dummy gate lines to electrically connect the lower dummy contact plug to the pair of dummy gate lines.
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