公开(公告)号：US20210257264A1

公开(公告)日：2021-08-19

申请号：US17246778

申请日：2021-05-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SANGMIN YOO ,  JUYOUN KIM ,  HYUNGJOO NA ,  BONGSEOK SUH ,  JOOHO JUNG ,  EUICHUL HWANG ,  SUNGMOON LEE

IPC: H01L21/8238 ,  H01L27/118 ,  H01L21/762

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate including an active pattern, a gate electrode extending in a first direction and crossing the active pattern which extends in a second direction, a separation structure crossing the active pattern and extending in the first direction, a first gate dielectric pattern disposed on a side surface of the gate electrode, a second gate dielectric pattern disposed on a side surface of the separation structure, and a gate capping pattern covering a top surface of the gate electrode. A level of a top surface of the separation structure is higher than a level of a top surface of the gate capping pattern.

公开(公告)号：US20240047339A1

公开(公告)日：2024-02-08

申请号：US18106540

申请日：2023-02-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SEUNGMIN CHA ,  SEUNGMIN SONG ,  YOUNGWOO KIM ,  JINKYU KIM ,  SORA YOU ,  NAMHYUN LEE ,  SUNGMOON LEE

IPC: H01L23/50 ,  H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L27/092 ,  H01L29/423 ,  H01L23/535 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L23/50 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/66545 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/4236 ,  H01L23/535 ,  H01L23/5226 ,  H01L23/5286

Abstract: An integrated circuit device includes a substrate, having a front surface and a rear surface opposite to each other, and a fin-type active region defined by a trench in the front surface, a device separation layer filling the trench, a source/drain region on the fin-type active region, a first conductive plug arranged on the source/drain region and electrically connected to the source/drain region, a power wiring line at least partially arranged on a lower surface of the substrate, a buried rail connected to the power wiring line through the device separation layer and decreasing in horizontal width toward the power wiring line, and a power via connecting the buried rail to the first conductive plug.

公开(公告)号：US20250089297A1

公开(公告)日：2025-03-13

申请号：US18621413

申请日：2024-03-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JEEWOONG KIM ,  SUNGMOON LEE ,  YUNSUK NAM ,  KEUN HWI CHO

IPC: H01L29/417 ,  H01L21/285 ,  H01L23/528 ,  H01L29/06 ,  H01L29/08 ,  H01L29/40 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L29/775

Abstract: A semiconductor device according to embodiment includes: a base insulation layer having a first surface and a second surface facing each other with a thickness therebetween; a channel layer on the first surface of the base insulation layer; a first source/drain pattern and a second source/drain pattern on the first surface of the base insulation layer and arranged in a first direction with the channel layer therebetween; a gate structure, that extends in a second direction crossing the first direction on the first surface of the base insulation layer, and surrounds the channel layer; a first silicide layer on a side wall of a recess pattern that penetrates the first source/drain pattern in a third direction that is perpendicular to the first direction and the second direction; and an interlayer insulation layer that is disposed in the recess pattern.

公开(公告)号：US20230253264A1

公开(公告)日：2023-08-10

申请号：US18300983

申请日：2023-04-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SANGMIN YOO ,  JUYOUN KIM ,  HYUNGJOO NA ,  BONGSEOK SUH ,  JOOHO JUNG ,  EUICHUL HWANG ,  SUNGMOON LEE

IPC: H01L21/8238 ,  H01L27/118 ,  H01L21/762

CPC classification number: H01L21/823878 ,  H01L27/11807 ,  H01L21/76224 ,  H01L2027/11861 ,  H01L2027/11829 ,  H01L2027/11816

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate including an active pattern, a gate electrode extending in a first direction and crossing the active pattern which extends in a second direction, a separation structure crossing the active pattern and extending in the first direction, a first gate dielectric pattern disposed on a side surface of the gate electrode, a second gate dielectric pattern disposed on a side surface of the separation structure, and a gate capping pattern covering a top surface of the gate electrode. A level of a top surface of the separation structure is higher than a level of a top surface of the gate capping pattern.