公开(公告)号：US20170011967A1

公开(公告)日：2017-01-12

申请号：US15171120

申请日：2016-06-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Hyun YEO ,  Jae-Suk KWON ,  Kwang-Woo LEE ,  Eun-Seong LEE

IPC: H01L21/8238 ,  H01L21/324 ,  H01L29/66 ,  H01L21/265

CPC classification number: H01L21/823814 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/324 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823821 ,  H01L21/823864 ,  H01L21/823871 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7833

Abstract: A method of manufacturing a semiconductor device includes forming a first gate structure on a substrate, the first gate structure including a gate insulation layer, a gate electrode, and a hard mask sequentially stacked on the substrate, forming a preliminary spacer layer on sidewalls of the first gate structure and the substrate, the preliminary spacer layer including silicon nitride, implanting molecular ions into the preliminary spacer layer to form a spacer layer having a dielectric constant lower than a dielectric constant of the preliminary spacer layer, anisotropically etching the spacer layer to form spacers on the sidewalls of the first gate structure, and forming impurity regions at upper portions of the substrate adjacent to the first gate structure.

Abstract translation: 一种制造半导体器件的方法包括在衬底上形成第一栅极结构，所述第一栅极结构包括依次层叠在所述衬底上的栅极绝缘层，栅电极和硬掩模，在所述衬底的侧壁上形成预备间隔层 第一栅极结构和衬底，初步间隔层包括氮化硅，将分子离子注入到初步间隔层中以形成介电常数低于预备间隔层的介电常数的间隔层，各向异性地蚀刻间隔层以形成 在第一栅极结构的侧壁上的间隔物，以及在与第一栅极结构相邻的衬底的上部处形成杂质区。