公开(公告)号：US20210225648A1

公开(公告)日：2021-07-22

申请号：US17224609

申请日：2021-04-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chang-woo NOH ,  Myung-gil KANG ,  Ho-jun KIM ,  Geum-jong BAE ,  Dong-il BAE

IPC: H01L21/02 ,  H01L21/762 ,  H01L29/78 ,  H01L29/165 ,  H01L21/768 ,  H01L29/06 ,  H01L29/423

Abstract: A semiconductor device according to an example embodiment includes a substrate extending in first and second directions intersecting with each other; nanowires on the substrate and spaced apart from each other in the second direction; gate electrodes extending in the first direction and spaced apart from each other in the second direction, and surrounding the nanowires to be superimposed vertically with the nanowires; external spacers on the substrate and covering sidewalls of the gate electrodes on the nanowires; and an isolation layer between the gate electrodes and extending in the first direction, wherein an upper surface of the isolation layer is flush with upper surfaces of the gate electrodes.

公开(公告)号：US20200051981A1

公开(公告)日：2020-02-13

申请号：US16257913

申请日：2019-01-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-gil YANG ,  Sang-su KIM ,  Sun-wook KIM ,  Geum-jong BAE ,  Seung-min SONG ,  Soo-jin JEONG

IPC: H01L27/092 ,  H01L29/08 ,  H01L29/06 ,  H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L21/02 ,  H01L21/8238

Abstract: A semiconductor device includes: a fin-type active area extending in a first direction protruding from a substrate; a plurality of nanosheet stacked structures; a blocking film covering a part of the upper surface and one sidewall of each of a pair of nanosheet stacked structures adjacent to both sides of the fin-type active area among the plurality of nanosheet stacked structures; a gate electrode extending in a second direction intersecting the first direction on the fin-type active area, the gate electrode including a real gate electrode surrounding the plurality of nanosheets and a dummy gate electrode disposed on the blocking film; and a gate dielectric layer between the real gate electrode and the plurality of nanosheets and between the dummy gate electrode and the blocking film.

公开(公告)号：US20210242201A1

公开(公告)日：2021-08-05

申请号：US17150712

申请日：2021-01-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myung-gil KANG ,  Beom-jin PARK ,  Geum-jong BAE ,  Dong-won KIM ,  Jung-gil YANG

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/308

Abstract: An integrated circuit (IC) device includes: a fin-type active area protruding from a substrate and extending in a first horizontal direction; a first nanosheet disposed above an upper surface of the fin-type active area with a first separation space therebetween; a second nanosheet disposed above the first nanosheet with a second separation space therebetween; a gate line extending on the substrate in a second horizontal direction intersecting the first horizontal direction, at least a portion of the gate line being disposed in the second separation space; and a bottom insulation structure disposed in the first separation space.

公开(公告)号：US20200075331A1

公开(公告)日：2020-03-05

申请号：US16361914

申请日：2019-03-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chang-woo NOH ,  Myung-gil KANG ,  Ho-jun KIM ,  Geum-jong BAE ,  Dong-il BAE

IPC: H01L21/02 ,  H01L21/762 ,  H01L21/768 ,  H01L29/165 ,  H01L29/78

Abstract: A semiconductor device according to an example embodiment includes a substrate extending in first and second directions intersecting with each other; nanowires on the substrate and spaced apart from each other in the second direction; gate electrodes extending in the first direction and spaced apart from each other in the second direction, and surrounding the nanowires to be superimposed vertically with the nanowires; external spacers on the substrate and covering sidewalls of the gate electrodes on the nanowires; and an isolation layer between the gate electrodes and extending in the first direction, wherein an upper surface of the isolation layer is flush with upper surfaces of the gate electrodes.