公开(公告)号：US12009404B2

公开(公告)日：2024-06-11

申请号：US17686504

申请日：2022-03-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungseok Ha ,  Gukil An ,  Keun Hwi Cho ,  Sungmin Kim

IPC: H01L29/51 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786

CPC classification number: H01L29/516 ,  H01L29/42364 ,  H01L29/42392 ,  H01L29/4966 ,  H01L29/78696

Abstract: Semiconductor devices and methods of forming the same are provided. The semiconductor devices may include a substrate, a pair of semiconductor patterns adjacent to each other on the substrate, a gate electrode on the pair of semiconductor patterns, a source/drain pattern connected to the pair of semiconductor patterns, and a ferroelectric pattern on surfaces of the pair of semiconductor patterns. The surfaces of the pair of semiconductor patterns may face each other, and the ferroelectric pattern may define a first space between the pair of semiconductor patterns. The gate electrode may include a work function metal pattern that is in the first space.

公开(公告)号：US11296204B2

公开(公告)日：2022-04-05

申请号：US16418705

申请日：2019-05-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungseok Ha ,  Gukil An ,  Keun Hwi Cho ,  Sungmin Kim

IPC: H01L29/51 ,  H01L29/49 ,  H01L29/786 ,  H01L29/423

Abstract: Semiconductor devices and methods of forming the same are provided. The semiconductor devices may include a substrate, a pair of semiconductor patterns adjacent to each other on the substrate, a gate electrode on the pair of semiconductor patterns, a source/drain pattern connected to the pair of semiconductor patterns, and a ferroelectric pattern on surfaces of the pair of semiconductor patterns. The surfaces of the pair of semiconductor patterns may face each other, and the ferroelectric pattern may define a first space between the pair of semiconductor patterns. The gate electrode may include a work function metal pattern that is in the first space.

公开(公告)号：US10957373B2

公开(公告)日：2021-03-23

申请号：US16428184

申请日：2019-05-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Keun Hwi Cho ,  Seunghan Park ,  Hyo-Jin Kim ,  Gukil An

IPC: G11C11/22 ,  H01L29/51 ,  H01L27/11502

Abstract: A semiconductor memory device includes a memory cell array including memory cells, a row decoder connected to the memory cell array through first conductive lines, write drivers and sense amplifiers connected to the memory cell array through second conductive lines, a voltage generator that supplies a first voltage to the row decoder and supplies a second voltage to the write drivers and sense amplifiers, and a data buffer that is connected to the write drivers and sense amplifiers and transfers data between the write drivers and sense amplifiers and an external device. At least one of the row decoder, the write drivers and sense amplifiers, the voltage generator, and the data buffer includes a first ferroelectric capacitor to amplify a voltage.