公开(公告)号：US20180075929A1

公开(公告)日：2018-03-15

申请号：US15699412

申请日：2017-09-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HOONKI KIM ,  Yongho Kim ,  Changnam Park ,  Taejoong Song ,  Woojin Rim ,  Jonghoom Jung

IPC: G11C29/00 ,  G11C5/02 ,  G11C7/10 ,  G11C29/26

CPC classification number: G11C29/702 ,  G11C5/025 ,  G11C7/1012 ,  G11C29/26 ,  G11C29/76 ,  G11C29/838

Abstract: A memory device includes a memory cell array including a plurality of memory cells arranged in a plurality of columns including a normal column and a redundancy column for repairing the normal column, a plurality of peripheral logic circuits including a normal peripheral logic circuit and a redundancy peripheral logic circuit for repairing the normal peripheral logic circuit, and a first path selection logic circuit configured to form first paths between the plurality of columns and the plurality of peripheral logic circuits, based on at least one defect from among a defect in at least one of the plurality of columns or a defect in at least one of the plurality of peripheral logic circuits.

公开(公告)号：US20180068715A1

公开(公告)日：2018-03-08

申请号：US15611274

申请日：2017-06-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HOONKI KIM ,  JONGHOON JUNG ,  YONGHO KIM

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C11/412

Abstract: A semiconductor memory device including: a first transistor connected between a first node and ground, the first transistor having a gate connected to a second node; a second transistor connected between the second node and ground, the second transistor having a gate connected to the first node; a third transistor connected between first and third nodes, the third transistor having a gate connected to the second node; a fourth transistor connected between second and fourth nodes, the fourth transistor having a gate connected to the first node; a fifth transistor connected between the first node and bit line, the fifth transistor having a gate connected to a word line; a sixth transistor connected between the second node and complementary bit line, the sixth transistor having a gate connected to the word line; and a circuit to reduce a gate-source voltage of the third or fourth transistor in a write operation.