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公开(公告)号：US10916535B2
公开(公告)日：2021-02-09
申请号：US16727280
申请日：2019-12-26
发明人： Jung-Ho Do , Woojin Rim , Jisu Yu , Jonghoon Jung
IPC分类号： H01L27/02 , H01L23/528 , G03F1/36 , H01L23/522 , H01L27/118 , H01L21/8238 , H01L23/485 , H01L27/092 , G06F30/398 , G06F119/18
摘要： A semiconductor device includes a substrate having a plurality of active patterns. A plurality of gate electrodes intersects the plurality of active patterns. An active contact is electrically connected to the active patterns. A plurality of vias includes a first regular via and a first dummy via. A plurality of interconnection lines is disposed on the vias. The plurality of interconnection lines includes a first interconnection line disposed on both the first regular via and the first dummy via. The first interconnection line is electrically connected to the active contact through the first regular via. Each of the vias includes a via body portion and a via barrier portion covering a bottom surface and sidewalls of the via body portion. Each of the interconnection lines includes an interconnection line body portion and an interconnection line barrier portion covering a bottom surface and sidewalls of the interconnection line body portion.
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公开(公告)号：US20180350791A1
公开(公告)日：2018-12-06
申请号：US15870143
申请日：2018-01-12
发明人： Jung-Ho Do , Woojin Rim , Jisu Yu , Jonghoon Jung
IPC分类号： H01L27/02 , H01L27/092 , H01L23/522 , H01L23/528 , G06F17/50 , G03F1/36
CPC分类号： H01L27/0207 , G03F1/36 , G06F17/5081 , G06F2217/12 , H01L21/823871 , H01L21/823878 , H01L23/485 , H01L23/5223 , H01L23/5226 , H01L23/528 , H01L23/5286 , H01L27/092 , H01L27/11807 , H01L2027/11875 , H01L2027/11881
摘要： A semiconductor device includes a substrate having a plurality of active patterns. A plurality of gate electrodes intersects the plurality of active patterns. An active contact is electrically connected to the active patterns. A plurality of vias includes a first regular via and a first dummy via. A plurality of interconnection lines is disposed on the vias. The plurality of interconnection lines includes a first interconnection line disposed on both the first regular via and the first dummy via. The first interconnection line is electrically connected to the active contact through the first regular via. Each of the vias includes a via body portion and a via barrier portion covering a bottom surface and sidewalls of the via body portion. Each of the interconnection lines includes an interconnection line body portion and an interconnection line barrier portion covering a bottom surface and sidewalls of the interconnection line body portion.
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公开(公告)号：US20210143144A1
公开(公告)日：2021-05-13
申请号：US17154282
申请日：2021-01-21
发明人： Jung-Ho Do , Woojin Rim , Jisu Yu , Jonghoon Jung
IPC分类号： H01L27/02 , H01L23/528 , G03F1/36 , H01L23/522 , H01L27/118 , H01L21/8238 , H01L23/485 , H01L27/092 , G06F30/398
摘要： A semiconductor device includes a substrate having a plurality of active patterns. A plurality of gate electrodes intersects the plurality of active patterns. An active contact is electrically connected to the active patterns. A plurality of vias includes a first regular via and a first dummy via. A plurality of interconnection lines is disposed on the vias. The plurality of interconnection lines includes a first interconnection line disposed on both the first regular via and the first dummy via. The first interconnection line is electrically connected to the active contact through the first regular via. Each of the vias includes a via body portion and a via barrier portion covering a bottom surface and sidewalls of the via body portion. Each of the interconnection lines includes an interconnection line body portion and an interconnection line barrier portion covering a bottom surface and sidewalls of the interconnection line body portion.
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公开(公告)号：US10332870B2
公开(公告)日：2019-06-25
申请号：US15870143
申请日：2018-01-12
发明人： Jung-Ho Do , Woojin Rim , Jisu Yu , Jonghoon Jung
IPC分类号： H01L27/02 , H01L27/092 , H01L23/522 , G06F17/50 , G03F1/36 , H01L23/528 , H01L21/8238 , H01L23/485 , H01L27/118
摘要： A semiconductor device includes a substrate having a plurality of active patterns. A plurality of gate electrodes intersects the plurality of active patterns. An active contact is electrically connected to the active patterns. A plurality of vias includes a first regular via and a first dummy via. A plurality of interconnection lines is disposed on the vias. The plurality of interconnection lines includes a first interconnection line disposed on both the first regular via and the first dummy via. The first interconnection line is electrically connected to the active contact through the first regular via. Each of the vias includes a via body portion and a via barrier portion covering a bottom surface and sidewalls of the via body portion. Each of the interconnection lines includes an interconnection line body portion and an interconnection line barrier portion covering a bottom surface and sidewalls of the interconnection line body portion.
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公开(公告)号：US11557585B2
公开(公告)日：2023-01-17
申请号：US17154282
申请日：2021-01-21
发明人： Jung-Ho Do , Woojin Rim , Jisu Yu , Jonghoon Jung
IPC分类号： H01L27/02 , H01L23/528 , G03F1/36 , H01L23/522 , H01L27/118 , H01L21/8238 , H01L23/485 , H01L27/092 , G06F30/398 , G06F119/18
摘要： A semiconductor device includes a substrate having a plurality of active patterns. A plurality of gate electrodes intersects the plurality of active patterns. An active contact is electrically connected to the active patterns. A plurality of vias includes a first regular via and a first dummy via. A plurality of interconnection lines is disposed on the vias. The plurality of interconnection lines includes a first interconnection line disposed on both the first regular via and the first dummy via. The first interconnection line is electrically connected to the active contact through the first regular via. Each of the vias includes a via body portion and a via barrier portion covering a bottom surface and sidewalls of the via body portion. Each of the interconnection lines includes an interconnection line body portion and an interconnection line barrier portion covering a bottom surface and sidewalls of the interconnection line body portion.
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公开(公告)号：US10134486B2
公开(公告)日：2018-11-20
申请号：US15699412
申请日：2017-09-08
发明人： Hoonki Kim , Yongho Kim , Changnam Park , Taejoong Song , Woojin Rim , Jonghoon Jung
摘要： A memory device includes a memory cell array including a plurality of memory cells arranged in a plurality of columns including a normal column and a redundancy column for repairing the normal column, a plurality of peripheral logic circuits including a normal peripheral logic circuit and a redundancy peripheral logic circuit for repairing the normal peripheral logic circuit, and a first path selection logic circuit configured to form first paths between the plurality of columns and the plurality of peripheral logic circuits, based on at least one defect from among a defect in at least one of the plurality of columns or a defect in at least one of the plurality of peripheral logic circuits.
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7.发明授权Memory device of a single-ended bitline structure including reference voltage generator 有权包含参考电压发生器的单端位线结构的存储器件公开(公告)号：US09524772B2
公开(公告)日：2016-12-20
申请号：US14793053
申请日：2015-07-07
发明人： Woojin Rim , Taejoong Song , Gyuhong Kim , Jongsun Park , Woong Choi
IPC分类号： G11C5/06 , G11C7/06 , G11C5/14 , G11C7/02 , G11C8/00 , G11C11/419 , G11C11/412 , G11C7/12
CPC分类号： G11C11/419 , G11C7/12 , G11C11/412 , G11C2207/002
摘要： A memory device includes a first memory cell array including memory cells of a single-ended bitline structure, a second memory cell array including memory cells of a single-ended bitline structure, a reference voltage generator configured to output a bitline voltage of a selected one of the first and second memory cell arrays as a sensing voltage according to an array select signal and output a bitline voltage of an unselected memory cell array as a reference voltage, and a differential sense amplifier configured to amplify and output a difference between the sensing voltage and the reference voltage. Logic states of the sensing voltage and the reference voltage are complementary to each other.
摘要翻译： 存储器件包括包括单端位线结构的存储器单元的第一存储单元阵列，包括单端位线结构的存储单元的第二存储单元阵列，配置为输出所选择的位线的位线电压的参考电压发生器 的第一和第二存储单元阵列作为根据阵列选择信号的感测电压，并输出未选择的存储单元阵列的位线电压作为参考电压;以及差分读出放大器，被配置为放大和输出感测电压 和参考电压。 感测电压和参考电压的逻辑状态彼此互补。
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公开(公告)号：US10020048B2
公开(公告)日：2018-07-10
申请号：US15361599
申请日：2016-11-28
发明人： Woojin Rim , Tae Joong Song , Yong Ho Kim , Sung Hyun Park
IPC分类号： G11C11/00 , G11C11/419 , G11C11/418 , G06F1/32 , G11C8/08
CPC分类号： G11C11/419 , G06F1/3275 , G11C8/08 , G11C11/418 , Y02D10/14
摘要： An integrated circuit (IC) and a mobile device are provided. The IC includes a memory cell that includes a word line, a bit line pair, and a storage cell connected to the word line and the bit line pair. The IC further includes a timing control circuit configured to generate switch signals based on an operation control signal, and a switch circuit configured to receive a first voltage, a second voltage and a third voltage having different levels, and output, to the word line, one among the first voltage, the second voltage, and the third voltage based on the switch signals.
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公开(公告)号：US20180075929A1
公开(公告)日：2018-03-15
申请号：US15699412
申请日：2017-09-08
发明人： HOONKI KIM , Yongho Kim , Changnam Park , Taejoong Song , Woojin Rim , Jonghoom Jung
CPC分类号： G11C29/702 , G11C5/025 , G11C7/1012 , G11C29/26 , G11C29/76 , G11C29/838
摘要： A memory device includes a memory cell array including a plurality of memory cells arranged in a plurality of columns including a normal column and a redundancy column for repairing the normal column, a plurality of peripheral logic circuits including a normal peripheral logic circuit and a redundancy peripheral logic circuit for repairing the normal peripheral logic circuit, and a first path selection logic circuit configured to form first paths between the plurality of columns and the plurality of peripheral logic circuits, based on at least one defect from among a defect in at least one of the plurality of columns or a defect in at least one of the plurality of peripheral logic circuits.
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公开(公告)号：US20160042785A1
公开(公告)日：2016-02-11
申请号：US14793053
申请日：2015-07-07
发明人： Woojin Rim , Taejoong Song , Gyuhong Kim , Jongsun Park , Woong Choi
IPC分类号： G11C11/419 , G11C11/418
CPC分类号： G11C11/419 , G11C7/12 , G11C11/412 , G11C2207/002
摘要： A memory device includes a first memory cell array including memory cells of a single-ended bitline structure, a second memory cell array including memory cells of a single-ended bitline structure, a reference voltage generator configured to output a bitline voltage of a selected one of the first and second memory cell arrays as a sensing voltage according to an array select signal and output a bitline voltage of an unselected memory cell array as a reference voltage, and a differential sense amplifier configured to amplify and output a difference between the sensing voltage and the reference voltage. Logic states of the sensing voltage and the reference voltage are complementary to each other.
摘要翻译： 存储器件包括包括单端位线结构的存储器单元的第一存储单元阵列，包括单端位线结构的存储单元的第二存储单元阵列，配置为输出所选择的位线的位线电压的参考电压发生器 的第一和第二存储单元阵列作为根据阵列选择信号的感测电压，并输出未选择的存储单元阵列的位线电压作为参考电压;以及差分读出放大器，被配置为放大和输出感测电压 和参考电压。 感测电压和参考电压的逻辑状态彼此互补。
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