公开(公告)号：US20140068160A1

公开(公告)日：2014-03-06

申请号：US14014511

申请日：2013-08-30

申请人： KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY ,  SAMSUNG ELECTRONICS CO., LTD.

发明人： HYE JEONG SO ,  SAE YOUNG CHUNG ,  JUN JIN KONG ,  CHANG KYU SEOL

IPC分类号： G06F12/02

CPC分类号： G06F12/0246 ,  G06F3/0659 ,  G06F2212/1036 ,  G06F2212/7202 ,  G06F2212/7204

摘要： A memory controller controls operation of a nonvolatile memory device comprising a memory area comprising a plurality of multi-level cells (MLCs). The memory controller receives an address of the memory area and data to be programmed to the memory area, analyzes access history information regarding the memory area based on the address, generates first mapping data corresponding to the data or second mapping data based on the data and previous mapping data that has been programmed to the MLCs according to a result of the analysis, and transmits a program command comprising one of the first mapping data and the second mapping data to the nonvolatile memory device.

摘要翻译： 存储器控制器控制包括包括多个多电平单元（MLC）的存储器区域的非易失性存储器件的操作。 存储器控制器接收存储器区域的地址和要编程到存储器区域的数据，基于地址分析关于存储器区域的访问历史信息，基于数据生成与数据或第二映射数据相对应的第一映射数据，以及 根据分析结果已经编程到MLC的先前映射数据，并将包括第一映射数据和第二映射数据中的一个的程序命令发送到非易失性存储器件。

公开(公告)号：US20210133543A1

公开(公告)日：2021-05-06

申请号：US16778168

申请日：2020-01-31

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： JIN SOO LIM ,  CHANG KYU SEOL ,  JAE HUN JANG ,  HYE JEONG SO ,  HONG RAK SON ,  PIL SANG YOON

IPC分类号： G06N3/063 ,  G06N20/00 ,  G06F7/544 ,  G11C11/419

摘要： A storage device is provided including an interface circuit configured to receive application information from a host; a field programmable gate array (FPGA); a neural processing unit (NPU); and a central processing unit (CPU) configured to select a hardware image from among a plurality of hardware images stored in a memory using the application information, and reconfigure the FPGA using the selected hardware image. The NPU is configured to perform an operation using the reconfigured FPGA.