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    G-LDPC DECODER AND G-LDPC DECODING METHOD
    3.
    发明公开
    G-LDPC DECODER AND G-LDPC DECODING METHOD 审中-公开

    公开(公告)号：US20240106462A1

    公开(公告)日：2024-03-28

    申请号：US18141103

    申请日：2023-04-28

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dae-Yeol Yang ,  BOHWAN JUN ,  HONG RAK SON ,  GEUNYEONG YU ,  YOUNGJUN HWANG

    IPC: H03M13/11 ,  H03M13/00

    CPC classification number: H03M13/1111 ,  H03M13/611

    Abstract: a G-LDPC decoder is provided. The G-LDPC decoder includes: a generalized check node decoder configured to, in each of a plurality of iterations: group connected variable nodes into groups, the connected variable nodes being connected to an mth generalized check node among generalized check nodes; generate test patterns in each of one or more of the groups based on a first message received by the mth generalized check node from the connected variable nodes; and identify a value of a second message to be provided from the mth generalized check node to the connected variable nodes based on the test patterns; and a LDPC decoder circuitry configured to, in each of the iterations, update a value of an nth variable node, among the variable nodes, based on the second message received by the nth variable node from a generalized check node that is connected to the nth variable node.

    MEMORY CONTROLLER OPERATING METHOD OF MEMORY CONTROLLER AND MEMORY SYSTEM
    4.
    发明申请
    MEMORY CONTROLLER OPERATING METHOD OF MEMORY CONTROLLER AND MEMORY SYSTEM 有权

    公开(公告)号：US20210265005A1

    公开(公告)日：2021-08-26

    申请号：US17317506

    申请日：2021-05-11

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： MINUK KIM ,  BOHWAN JUN ,  HONG RAK SON ,  DONG-MIN SHIN ,  KIJUN LEE

    IPC: G11C29/42 ,  G06F11/10 ,  G06F3/06

    Abstract: An operating method of a memory controller that individually controls a plurality of memory units includes reading respective segments from the plurality of memory units based on a plurality of control signals; generating an output codeword based on the segments; performing error correction decoding on the output codeword; when a result of the error correction decoding indicates success, updating at least one of a plurality of accumulated error pattern information respectively corresponding to the plurality of memory units based on the result of the error correction decoding; and when the result of the error correction decoding indicates failure, regulating at least one of the plurality of control signals based on at least one of the plurality of accumulated error pattern information.

    RESISTIVE MEMORY SYSTEM AND METHOD OF OPERATING THE RESISTIVE MEMORY SYSTEM
    7.
    发明申请
    RESISTIVE MEMORY SYSTEM AND METHOD OF OPERATING THE RESISTIVE MEMORY SYSTEM 有权
    电阻记忆系统和操作电阻记忆系统的方法

    公开(公告)号：US20160240252A1

    公开(公告)日：2016-08-18

    申请号：US15042516

    申请日：2016-02-12

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： EUN CHU OH ,  JUN JIN KONG ,  YOUNG BAE KIM ,  HONG RAK SON ,  PIL SANG YOON ,  HAN SHIN SHIN

    IPC: G11C13/00

    CPC classification number: G11C13/0069 ,  G11C7/1006 ,  G11C11/1675 ,  G11C11/5607 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0035 ,  G11C13/004 ,  G11C13/0097 ,  G11C2013/0076

    Abstract: A resistive memory system having a plurality of memory cells includes a memory device having a resistive memory cell array and a controller. The controller generates write data to be written to the memory cell array by encoding input data such that the input data corresponds to an erase state and a plurality of programming states that a memory cell may have. The input data is encoded such that at least one of the number of memory cells assigned a first programming state and the number of memory cells assigned a second programming state is smaller than at least one of the numbers of memory cells in the erase state and the other programming states. The first programming state has a highest resistance level among the plurality of programming states, and the second programming state has a second highest resistance level among the plurality of programming states.

    Abstract translation: 具有多个存储单元的电阻式存储器系统包括具有电阻性存储单元阵列和控制器的存储器件。 控制器通过对输入数据进行编码来产生要写入存储单元阵列的写入数据，使得输入数据对应于存储单元可能具有的擦除状态和多个编程状态。 编码输入数据使得分配了第一编程状态的存储器单元的数量和分配有第二编程状态的存储单元的数量中的至少一个小于擦除状态下的至少一个存储单元，并且 其他编程状态。 第一编程状态在多个编程状态中具有最高的电阻电平，并且第二编程状态在多个编程状态中具有第二高的电阻电平。

    MEMORY CONTROLLER AND METHOD OF OPERATING THE SAME
    9.
    发明申请
    MEMORY CONTROLLER AND METHOD OF OPERATING THE SAME 有权
    记忆控制器及其操作方法

    公开(公告)号：US20140281816A1

    公开(公告)日：2014-09-18

    申请号：US14205478

    申请日：2014-03-12

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： MOSHE SCHWARTZ ,  HONG RAK SON ,  JUN JIN KONG ,  JUNG SOO CHUNG

    IPC: G06F11/10

    CPC classification number: G06F17/2223 ,  G06F11/004 ,  G06F11/1072 ,  G06F17/2217 ,  H03M13/152 ,  H03M13/2906

    Abstract: A method of operating a memory controller is provided. The method includes determining a data state based on an input stream including multiple alphabet letters, converting a part of the input stream, which corresponds to a conversion size, into alphabet letters in a lower numeral system when the data state is determined to be a first state among multiple predetermined data states, inserting one of the converted alphabet letters into the input stream, and outputting each of the alphabet letters in the input stream as is when the data state is determined to be a second state among the predetermined data states.

    Abstract translation: 提供了一种操作存储器控制器的方法。 该方法包括：当数据状态被确定为第一个时，基于包括多个字母表的输入流确定数据状态，将与转换大小对应的输入流的一部分转换成较低数字系统中的字母 在多个预定数据状态中，将所转换的字母字母之一插入到输入流中，并且在数据状态被确定为预定数据状态之间的第二状态时输出输入流中的每个字母。

    STORAGE DEVICE AND OPERATING METHOD OF STORAGE DEVICE
    10.
    发明申请
    STORAGE DEVICE AND OPERATING METHOD OF STORAGE DEVICE 有权

    公开(公告)号：US20210202012A1

    公开(公告)日：2021-07-01

    申请号：US16990262

    申请日：2020-08-11

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： HYUNSEUNG HAN ,  SEONGHYEOG CHOI ,  YOUNGSUK RA ,  HONG RAK SON ,  TAEHYUN SONG ,  BOHWAN JUN

    IPC: G11C16/26 ,  G06F11/10 ,  H03M13/11 ,  G06F3/06 ,  G11C16/10

    Abstract: A storage device includes a nonvolatile memory device and a memory controller. The memory controller receives first data from the nonvolatile memory device based on a first read command, and performs error correction on the first data. When the error correction fails, the memory controller transmits a second read command and second read voltage information to the nonvolatile memory device, receives second data from the nonvolatile memory device, transmits a third read command and third read voltage information to the nonvolatile memory device, and receives third data from the nonvolatile memory device. The memory controller adjusts an offset based on the second data and the third data, transmits a fourth read command, fourth read voltage information, and the offset to the nonvolatile memory device, receives fourth data from the nonvolatile memory device, and performs a soft decision process based on the fourth data.

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