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1.发明申请公开(公告)号：US20160240252A1
公开(公告)日：2016-08-18
申请号：US15042516
申请日：2016-02-12
发明人： EUN CHU OH , JUN JIN KONG , YOUNG BAE KIM , HONG RAK SON , PIL SANG YOON , HAN SHIN SHIN
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C7/1006 , G11C11/1675 , G11C11/5607 , G11C11/5678 , G11C11/5685 , G11C13/0035 , G11C13/004 , G11C13/0097 , G11C2013/0076
摘要： A resistive memory system having a plurality of memory cells includes a memory device having a resistive memory cell array and a controller. The controller generates write data to be written to the memory cell array by encoding input data such that the input data corresponds to an erase state and a plurality of programming states that a memory cell may have. The input data is encoded such that at least one of the number of memory cells assigned a first programming state and the number of memory cells assigned a second programming state is smaller than at least one of the numbers of memory cells in the erase state and the other programming states. The first programming state has a highest resistance level among the plurality of programming states, and the second programming state has a second highest resistance level among the plurality of programming states.
摘要翻译： 具有多个存储单元的电阻式存储器系统包括具有电阻性存储单元阵列和控制器的存储器件。 控制器通过对输入数据进行编码来产生要写入存储单元阵列的写入数据，使得输入数据对应于存储单元可能具有的擦除状态和多个编程状态。 编码输入数据使得分配了第一编程状态的存储器单元的数量和分配有第二编程状态的存储单元的数量中的至少一个小于擦除状态下的至少一个存储单元，并且 其他编程状态。 第一编程状态在多个编程状态中具有最高的电阻电平，并且第二编程状态在多个编程状态中具有第二高的电阻电平。
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公开(公告)号：US20140269057A1
公开(公告)日：2014-09-18
申请号：US14211077
申请日：2014-03-14
发明人： YOAV SHERESHEVSKI , AVNER DOR , SHMUEL DASHEVSKY , JUN JIN KONG , PIL SANG YOON
IPC分类号： G11C16/10
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/3459
摘要： A method of programming a non-volatile memory device includes; defining a set of verification voltages, setting a maximum verification voltage among verification voltages that are less than or equal to a first target programming voltage to be a target verification voltage, calculating a number of extra pulses based on the target verification voltage and the first target programming voltage, verifying whether a threshold voltage of the memory cell is equal to or greater than the target verification voltage by applying an incremental step pulse program (ISPP) pulse to the memory cell and then applying at least one verification voltage in the set of verification voltages to the memory cell, and further applying the ISPP pulse to the memory cell a number of times equal to the number of extra pulses when the threshold voltage is verified to be equal to or greater than the target verification voltage.
摘要翻译： 非易失性存储器件的编程方法包括： 定义一组验证电压，将小于或等于第一目标编程电压的验证电压之间的最大验证电压设置为目标验证电压，基于目标验证电压和第一目标计算额外脉冲数 编程电压，通过向存储单元施加增量步进脉冲程序（ISPP）脉冲，然后在验证集合中施加至少一个验证电压来验证存储器单元的阈值电压是否等于或大于目标验证电压 并且当阈值电压被验证为等于或大于目标验证电压时，进一步将ISPP脉冲施加到存储器单元等于额外脉冲数的次数。
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公开(公告)号：US20210336766A1
公开(公告)日：2021-10-28
申请号：US17145617
申请日：2021-01-11
发明人： KWANG HOON KIM , PIL SANG YOON
摘要： An operating method of a memory controller includes generating a random value using a seed, generating encrypted intermediate data by encrypting plaintext data using the random value, and storing the seed and the intermediate data in a memory device. Ciphertext data is generated using the seed and the intermediate data based on Ring Learning with Error (RLWE).
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公开(公告)号：US20210133543A1
公开(公告)日：2021-05-06
申请号：US16778168
申请日：2020-01-31
发明人： JIN SOO LIM , CHANG KYU SEOL , JAE HUN JANG , HYE JEONG SO , HONG RAK SON , PIL SANG YOON
IPC分类号： G06N3/063 , G06N20/00 , G06F7/544 , G11C11/419
摘要： A storage device is provided including an interface circuit configured to receive application information from a host; a field programmable gate array (FPGA); a neural processing unit (NPU); and a central processing unit (CPU) configured to select a hardware image from among a plurality of hardware images stored in a memory using the application information, and reconfigure the FPGA using the selected hardware image. The NPU is configured to perform an operation using the reconfigured FPGA.
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