Method of operating resistive memory device reducing read disturbance

    公开(公告)号:US10546637B2

    公开(公告)日:2020-01-28

    申请号:US16037109

    申请日:2018-07-17

    Abstract: A resistive memory device includes: a memory cell array including resistive memory cells disposed at respective intersections between word lines and bit lines, a first column selection circuit disposed on one side of the memory cell array and configured to selectively connect a bit line connected to a selected memory cell among the resistive memory cells, a second column selection circuit disposed on another side of the memory cell array opposite the first column selection circuit and configured to selectively connect the bit line connected to the selected memory cell, and a control circuit configured to determine a distant column selection circuit from among the first column selection circuit and the second column selection circuit relative to the selected memory cell, and enable the distant column selection circuit during a read operation directed to the selected memory.

    Method of operating resistive memory device reducing read disturbance

    公开(公告)号:US10770138B2

    公开(公告)日:2020-09-08

    申请号:US16721372

    申请日:2019-12-19

    Abstract: A resistive memory device includes: a memory cell array including resistive memory cells disposed at respective intersections between word lines and bit lines, a first column selection circuit disposed on one side of the memory cell array and configured to selectively connect a bit line connected to a selected memory cell among the resistive memory cells, a second column selection circuit disposed on another side of the memory cell array opposite the first column selection circuit and configured to selectively connect the bit line connected to the selected memory cell, and a control circuit configured to determine a distant column selection circuit from among the first column selection circuit and the second column selection circuit relative to the selected memory cell, and enable the distant column selection circuit during a read operation directed to the selected memory.

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