FLASH MEMORY DEVICE HAVING MULTI-STACK STRUCTURE AND CHANNEL SEPARATION METHOD THEREOF

    公开(公告)号:US20230145117A1

    公开(公告)日:2023-05-11

    申请号:US17982081

    申请日:2022-11-07

    CPC classification number: G11C16/102 G11C16/12 G11C16/08

    Abstract: A flash memory device is provided. The flash memory device includes: a first memory cell; a second memory cell on the first memory cell; and a third memory cell between the first memory cell and the second memory cell. The first memory cell, the second memory cell and the third memory cell share a channel. The third memory cell is configured to block channel sharing between the first memory cell and the second memory cell based on a channel separation voltage provided in first to k-th program loops. The third memory cell is configured to connect the channel sharing between the first memory cell and the second memory cell based on a channel connection voltage provided to the third memory cell in a (k+1)-th program loop.

Patent Agency Ranking