公开(公告)号：US12034060B2

公开(公告)日：2024-07-09

申请号：US17837158

申请日：2022-06-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hongsik Shin ,  Hyunjoon Roh ,  Heungsik Park ,  Sughyun Sung ,  Dohaing Lee ,  Wonhyuk Lee

IPC: H01L29/06 ,  H01L21/306 ,  H01L21/311 ,  H01L21/768 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/6656 ,  H01L21/30604 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76897 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823475 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/41791 ,  H01L29/4232 ,  H01L29/42392 ,  H01L29/66553 ,  H01L29/785 ,  H01L29/78696 ,  H01L2029/7858

Abstract: A semiconductor device includes a gate pattern crossing over a substrate, the gate pattern including a gate insulating layer, a gate electrode, and a gate capping pattern sequentially stacked on the substrate, a gate spacer covering a sidewall of the gate pattern, a source/drain pattern on the substrate, the source/drain pattern being adjacent to the sidewall of the gate pattern, a contact pad on the source/drain pattern, a top surface of the contact pad being lower than a top surface of the gate electrode, a source/drain contact plug on the contact pad, and a protection spacer between the gate spacer and the source/drain contact plug, the protection spacer having a ring shape enclosing the source/drain contact plug.

公开(公告)号：US11362196B2

公开(公告)日：2022-06-14

申请号：US16841889

申请日：2020-04-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hongsik Shin ,  Hyunjoon Roh ,  Heungsik Park ,  Sughyun Sung ,  Dohaing Lee ,  Wonhyuk Lee

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L27/088 ,  H01L29/78 ,  H01L21/768 ,  H01L21/311 ,  H01L21/306 ,  H01L21/8234

Abstract: A semiconductor device includes a gate pattern crossing over a substrate, the gate pattern including a gate insulating layer, a gate electrode, and a gate capping pattern sequentially stacked on the substrate, a gate spacer covering a sidewall of the gate pattern, a source/drain pattern on the substrate, the source/drain pattern being adjacent to the sidewall of the gate pattern, a contact pad on the source/drain pattern, a top surface of the contact pad being lower than a top surface of the gate electrode, a source/drain contact plug on the contact pad, and a protection spacer between the gate spacer and the source/drain contact plug, the protection spacer having a ring shape enclosing the source/drain contact plug.