公开(公告)号：US11948632B2

公开(公告)日：2024-04-02

申请号：US17497502

申请日：2021-10-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jungyu Lee ,  Hyunkook Parak ,  Jongryul Kim

IPC: G11C11/00 ,  G11C13/00

CPC classification number: G11C13/0004 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0038 ,  G11C13/0069

Abstract: A memory device includes a phase change memory (PCM) cell connected between a bit line and a word line. An X-decoder provides a word line voltage to the word line during a reset operation, and a Y-decoder provides a bit line voltage to the bit line during the reset operation. A voltage bias circuit generates the word line voltage and the bit line voltage based on a first bias during a first period of the reset operation, the word line voltage and the bit line voltage based on a second bias greater than the first bias during a second period of the reset operation, and the word line voltage and the bit line voltage based on a third bias smaller than the first and second biases during a third period of the reset operation.