公开(公告)号：US20240047328A1

公开(公告)日：2024-02-08

申请号：US18341345

申请日：2023-06-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinduck Park ,  Chansik Kwon ,  Yongseong Kim ,  Inwook Im ,  Jiyeon Han

IPC: H01L23/498 ,  H01L25/065 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/49822 ,  H01L25/0657 ,  H01L23/3107 ,  H01L23/49838 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/15153 ,  H01L2924/15184

Abstract: A semiconductor package includes a package base substrate including a substrate cavity formed therein, the substrate cavity extending from a top surface of the package base substrate downwardly toward a bottom surface of the package base substrate. The package base substrate further includes a plurality of base insulating layers, a plurality of substrate wiring patterns extending along at least one of a top surface and a bottom surface of each of the plurality of base insulating layers, and a plurality of substrate conductive vias which pass through at least one of the plurality of base insulating layers and are connected to the plurality of substrate wiring patterns. The semiconductor package further includes a plurality of semiconductor chips disposed at a bottom of the substrate cavity and stacked in a direction perpendicular to a plane of the package base substrate.