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Patent Agency Ranking
公开(公告)号：US20240137032A1
公开(公告)日：2024-04-25
申请号：US18348972
申请日：2023-07-06
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： JOO-HAN KIM , JUNGSU HAN , BEOM KON KIM , JOOHYUN DO
CPC classification number: H03M1/0607 , H03M1/0626 , H03M1/125
Abstract: A digital signal processing circuit includes an analog gain compensator that compensates for an analog gain of a baseband signal including a plurality of component carriers (CCs) to output a compensated baseband signal; an analog-to-digital converter (ADC) that converts the compensated baseband signal into a first digital signal; a plurality of filtering circuits that generate a second digital signal from the first digital signal; and a control circuit. Each filtering circuit sequentially filters the first digital signal so that a corresponding one of the second digital signals retains one CC among the CCs, compensates for a digital gain, and a performs down-sampling. The control circuit generates an analog gain control signal for controlling the analog gain based on the second digital signals and a digital gain control signal for controlling the digital gain.
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2.发明公开公开(公告)号：US20230292176A1
公开(公告)日：2023-09-14
申请号：US18319161
申请日：2023-05-17
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： SUNGYOON CHO , JOOHYUN DO
Abstract: A wireless communication apparatus includes a radio frequency integrated circuit (RFIC) configured to receive an input signal to generate a digital sample signal from the input signal, a data compressor configured to compress the digital sample signal according to a compression manner based on a data probability distribution of the input signal varying based on a receivable signal amplitude range of the RFIC, a data decompressor configured to decompress the compressed digital sample signal on the basis of a decompression manner corresponding to the compression manner to generate a decompressed digital sample signal, a data transfer link configured to transfer the compressed digital sample signal to the data decompressor, and a processor configured to process the decompressed digital sample signal.
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公开(公告)号：US20210092638A1
公开(公告)日：2021-03-25
申请号：US16925947
申请日：2020-07-10
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： SUNGYOON CHO , JOOHYUN DO
Abstract: A wireless communication apparatus includes a radio frequency integrated circuit (RFIC) configured to receive an input signal to generate a digital sample signal from the input signal, a data compressor configured to compress the digital sample signal according to a compression manner based on a data probability distribution of the input signal varying based on a receivable signal amplitude range of the RFIC, a data decompressor configured to decompress the compressed digital sample signal on the basis of a decompression manner corresponding to the compression manner to generate a decompressed digital sample signal, a data transfer link configured to transfer the compressed digital sample signal to the data decompressor, and a processor configured to process the decompressed digital sample signal.
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公开(公告)号：US20240235566A9
公开(公告)日：2024-07-11
申请号：US18348972
申请日：2023-07-07
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： JOO-HAN KIM , JUNGSU HAN , BEOM KON KIM , JOOHYUN DO
CPC classification number: H03M1/0607 , H03M1/0626 , H03M1/125
Abstract: A digital signal processing circuit includes an analog gain compensator that compensates for an analog gain of a baseband signal including a plurality of component carriers (CCs) to output a compensated baseband signal; an analog-to-digital converter (ADC) that converts the compensated baseband signal into a first digital signal; a plurality of filtering circuits that generate a second digital signal from the first digital signal; and a control circuit. Each filtering circuit sequentially filters the first digital signal so that a corresponding one of the second digital signals retains one CC among the CCs, compensates for a digital gain, and a performs down-sampling. The control circuit generates an analog gain control signal for controlling the analog gain based on the second digital signals and a digital gain control signal for controlling the digital gain.
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5.发明申请公开(公告)号：US20200169347A1
公开(公告)日：2020-05-28
申请号：US16685354
申请日：2019-11-15
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： SUNGYOON CHO , JOOHYUN DO , MYUNGJOON SHIM , HAECHUL LEE , BORA LIM , DAHAE CHONG , SEUNGJOONG HWANG
Abstract: An operating method of a terminal performing a cell search using first and second memories for buffering input samples includes detecting a first primary synchronization signal (PSS) group from a first input sample group while buffering the first input sample group in the first memory in a first interval. While buffering a second input sample group in the second memory in a second interval following the first interval, the method detects a second PSS group from the second input sample group, and a first secondary synchronization signal (SSS) group corresponding to the first PSS group from the first input sample group. While buffering a third input sample group in the first memory in a third interval following the second interval, the method detects a third PSS group from the third input sample group, and a second SSS group corresponding to the second PSS group from the second input sample group.
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