公开(公告)号：US11728961B2

公开(公告)日：2023-08-15

申请号：US17586182

申请日：2022-01-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyung Min Lee ,  Jae Hong Jung ,  Seung Jin Kim ,  Seung Hyun Oh

IPC: H04L7/00 ,  H04L7/033

CPC classification number: H04L7/0037 ,  H04L7/033

Abstract: A clock generating circuit includes a first frequency multiplier configured to generate a second clock signal having a second frequency based on a first clock signal having a first frequency, and a second frequency multiplier configured to generate a third clock signal having a third frequency based on the second clock signal. The first frequency multiplier includes a circuit configured to control a duty cycle of the first clock signal, a delay circuit configured to receive the duty controlled clock signal, and delay the received signal based on a duty cycle of the second clock signal to output a first delay clock signal, and an XOR gate configured to perform an XOR computation using the duty controlled clock signal and the first delay clock signal to output the second clock signal. The second frequency is greater than the first frequency, and the third frequency is greater than the second frequency.

公开(公告)号：US20220368513A1

公开(公告)日：2022-11-17

申请号：US17586182

申请日：2022-01-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyung Min Lee ,  Jae Hong Jung ,  Seung Jin Kim ,  Seung Hyun Oh

IPC: H04L7/00 ,  H04L7/033

Abstract: A clock generating circuit includes a first frequency multiplier configured to generate a second clock signal having a second frequency based on a first clock signal having a first frequency, and a second frequency multiplier configured to generate a third clock signal having a third frequency based on the second clock signal. The first frequency multiplier includes a circuit configured to control a duty cycle of the first clock signal, a delay circuit configured to receive the duty controlled clock signal, and delay the received signal based on a duty cycle of the second clock signal to output a first delay clock signal, and an XOR gate configured to perform an XOR computation using the duty controlled clock signal and the first delay clock signal to output the second clock signal. The second frequency is greater than the first frequency, and the third frequency is greater than the second frequency.