公开(公告)号：US20180294256A1

公开(公告)日：2018-10-11

申请号：US15842995

申请日：2017-12-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Inhak LEE ,  Sang-Yeop BAECK ,  JaeSeung CHOI ,  Hyunsu CHOI ,  SangShin HAN

IPC: H01L27/02 ,  H01L27/092 ,  H01L27/11 ,  H01L23/522 ,  H01L23/528 ,  H01L21/8238 ,  G06F17/50

CPC classification number: H01L27/0207 ,  G06F17/5081 ,  H01L21/823821 ,  H01L21/823871 ,  H01L23/5226 ,  H01L23/5286 ,  H01L27/0924 ,  H01L27/1104 ,  H01L29/7848

Abstract: A semiconductor device including memory cell transistors on a substrate is provided. The semiconductor device includes a first wiring layer on the memory cell transistors and including a bit line and a first conductive pattern, a second wiring layer on the first wiring layer and including a ground line, a first via interposed between and electrically connecting the bit line and a source/drain of a first memory cell transistor among the memory cell transistors, and a first extended via interposed between the ground line and a source/drain of a second memory cell transistor among the memory cell transistors. The ground line is electrically connected to the source/drain of the second memory cell transistor through the first extended via and the first conductive pattern. The first extended via has a width greater than that of the first via.