公开(公告)号：US20240161790A1

公开(公告)日：2024-05-16

申请号：US18203754

申请日：2023-05-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaehue SHIN ,  Yongsung CHO ,  Daeseok BYEON

IPC: G11C7/10 ,  G11C5/14 ,  G11C7/12

CPC classification number: G11C7/1057 ,  G11C5/14 ,  G11C7/1069 ,  G11C7/12

Abstract: A memory device includes a memory cell array including a plurality of memory cells, and a page buffer circuit including a plurality of page buffer units respectively connected with the memory cells through a plurality of bit lines. A sensing node is connected to a bit line for each buffer circuit. The plurality of page buffer units are respectively connected with sensing nodes, each of the plurality of page buffer units includes at least one transistor. One or more auxiliary wires in the proximity of the sensing node are used to reduce coupling problems caused by a low capacitance of the sensing node.