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公开(公告)号：US20220068399A1
公开(公告)日：2022-03-03
申请号：US17229053
申请日：2021-04-13
发明人： Yongsung CHO
摘要： A memory device for performing temperature compensation and an operating method thereof are provided. The memory device includes a memory cell array; a page buffer circuit connected to the memory cell array through a plurality of bit lines, including a page buffer connected to each of the plurality of bit lines, and configured to perform a pre-charge operation during a pre-charge period for data reading; and a control logic configured to differently control the pre-charge operation of the page buffer circuit according to a detected temperature, wherein the pre-charge period includes a first period in which the plurality of bit lines are overdriven and a second period in which the plurality of bit lines are driven at a voltage lower than that of the first period, and the first period where the detected temperature is a first temperature is set to be shorter than the second period where the detected temperature is a second temperature higher than the first temperature.
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公开(公告)号：US20240161790A1
公开(公告)日：2024-05-16
申请号：US18203754
申请日：2023-05-31
发明人： Jaehue SHIN , Yongsung CHO , Daeseok BYEON
CPC分类号： G11C7/1057 , G11C5/14 , G11C7/1069 , G11C7/12
摘要： A memory device includes a memory cell array including a plurality of memory cells, and a page buffer circuit including a plurality of page buffer units respectively connected with the memory cells through a plurality of bit lines. A sensing node is connected to a bit line for each buffer circuit. The plurality of page buffer units are respectively connected with sensing nodes, each of the plurality of page buffer units includes at least one transistor. One or more auxiliary wires in the proximity of the sensing node are used to reduce coupling problems caused by a low capacitance of the sensing node.
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公开(公告)号：US20230387889A1
公开(公告)日：2023-11-30
申请号：US18154966
申请日：2023-01-16
发明人： Hyunseok NAM , Jaehyuk YANG , Yongsung CHO
摘要： A clock generating device includes a first voltage output circuit configured to output a first voltage corresponding to a power supply voltage in response to a preliminary clock signal, a clock output circuit configured to generate the preliminary clock signal and a final clock signal at a period corresponding to a difference between the first voltage and a negative feedback voltage, a negative feedback voltage generating circuited configured to generate the negative feedback voltage from a reference value corresponding to a frequency of the final clock signal and a second voltage and filtered to a uniform voltage level, and a second voltage output circuit configured to output the second voltage to the negative feedback voltage generating unit, the second voltage having lower sensitivity of fluctuations in the power supply voltage than the first voltage.
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4.发明公开公开(公告)号：US20230230640A1
公开(公告)日：2023-07-20
申请号：US17960630
申请日：2022-10-05
发明人： Yongsung CHO , Min-Hwi KIM , Hosang CHO
IPC分类号： G11C16/26
CPC分类号： G11C16/26 , G11C16/0483
摘要： A cache read method of a nonvolatile memory device including a plurality of page buffer units and cache latches, each page buffer units having a sensing latch and a sensing node line is provided. The method comprises performing a first on-chip valley search (OVS) read on a selected memory cell using a first sensing node line and a first sensing latch of a first page buffer unit of the plurality of page buffer units; storing first data sensed from the selected memory cell in the first sensing latch, the first data based on a result of the first OVS read; dumping the first data to sensing node lines of at least one page buffer unit, excluding the first page buffer unit, from among the plurality of page buffer units; and performing a second OVS read on the selected memory cell using the first sensing latch.
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公开(公告)号：US20210343352A1
公开(公告)日：2021-11-04
申请号：US17134968
申请日：2020-12-28
发明人： Yongsung CHO , Bong-Kil JUNG , Hangil JEONG
摘要： An operating method of a nonvolatile memory device includes receiving, at the nonvolatile memory device, a suspend command, suspending, at the nonvolatile memory device, a program operation being performed, in response to the suspend command, receiving, at the nonvolatile memory device, a resume command, and resuming, at the nonvolatile memory device, the suspended program operation in response to the resume command. The program operation includes program loops, each of which includes a bit line setup interval, a program interval, and a verify interval. In the program interval of each of the program loops, a level of a program voltage to be applied to selected memory cells of the nonvolatile memory device increases as much as a first voltage. A difference between a level of the program voltage finally applied s suspend and a level of the program voltage applied first after resume is different from the first voltage.
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公开(公告)号：US20240331776A1
公开(公告)日：2024-10-03
申请号：US18743852
申请日：2024-06-14
发明人： Yongsung CHO
摘要： A memory device includes a memory cell array, and a page buffer circuit connected to the memory cell array through a plurality of bit lines, including a plurality of page buffers arranged in correspondence with the bit lines and each of which includes a sensing node. The plurality of page buffers include a first page buffer, and the first page buffer includes: a first sensing node configured to sense data by corresponding to a first metal wire at a lower metal layer; and a second metal wire electrically connected to the first metal wire and at an upper metal layer located above the lower metal layer, and a boost node corresponding to a third metal wire adjacent to the second metal wire of the upper metal layer and configured to control a boost-up and a boost-down of a voltage of the first sensing node.
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7.发明公开公开(公告)号：US20240265977A1
公开(公告)日：2024-08-08
申请号：US18366368
申请日：2023-08-07
发明人： Jongryul KIM , Yongsung CHO
CPC分类号： G11C16/30 , G11C16/0483 , G11C16/24
摘要： A flash memory device including a cell string including memory cells, a page buffer connected to the cell string and a bit line and configured to sense data stored in a selected memory cell by pre-charging a sensing node connected to the bit line, the page buffer including a latch including a latch node and an inverted latch node, a sampling switch circuit configured to perform a trip voltage sampling operation by electrically connecting the latch node and the sensing node according to a sampling control signal, and a pull-down NMOS transistor configured to define a trip voltage provided to the latch node based on a sensing result of the data stored in the selected memory cell, and a voltage regulator configured to adjust the trip voltage by providing a source voltage to the pull-down NMOS transistor of the page buffer, may be provided.
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8.发明公开公开(公告)号：US20230386539A1
公开(公告)日：2023-11-30
申请号：US18449864
申请日：2023-08-15
发明人： Yongsung CHO , Min Hwi KIM , Ji-Sang LEE
CPC分类号： G11C7/20 , G11C7/065 , G11C7/1039 , G11C7/12
摘要： Disclosed is a memory device which includes a memory cell array including memory cells, data latches connected with a sensing node and storing data in a first memory cell of the memory cells, a sensing latch connected with the sensing node, a temporary storage node, a switch connected between the sensing latch and the temporary storage node and configured to operate in response to a temporary storage node setup signal, a first precharge circuit configured to selectively precharge a first bit line corresponding to the first memory cell depending on a level of the temporary storage node, and a control logic circuit configured to control a dump operation between the data latches, the sensing latch, and the temporary storage node. The control logic circuit performs the dump operation from the data latches to the sensing latch while the first precharge circuit selectively precharges the first bit line.
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9.发明申请公开(公告)号：US20230060080A1
公开(公告)日：2023-02-23
申请号：US17888661
申请日：2022-08-16
发明人： Yongsung CHO , Min Hwi KIM , Ji-Sang LEE
摘要： Disclosed is a memory device which includes a memory cell array including memory cells, data latches connected with a sensing node and storing data in a first memory cell of the memory cells, a sensing latch connected with the sensing node, a temporary storage node, a switch connected between the sensing latch and the temporary storage node and configured to operate in response to a temporary storage node setup signal, a first precharge circuit configured to selectively precharge a first bit line corresponding to the first memory cell depending on a level of the temporary storage node, and a control logic circuit configured to control a dump operation between the data latches, the sensing latch, and the temporary storage node. The control logic circuit performs the dump operation from the data latches to the sensing latch while the first precharge circuit selectively precharges the first bit line.
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公开(公告)号：US20230055963A1
公开(公告)日：2023-02-23
申请号：US17710283
申请日：2022-03-31
发明人： Yongsung CHO , Kyoman Kang , Minhwi Kim , Ilhan Park , Jinyoung Chun
摘要： A memory device is provided. The memory device includes: a memory cell array including a plurality of memory cells; a page buffer circuit connected to the memory cell array through a plurality of bit lines and including a page buffer connected to each of the plurality of bit lines, the page buffer including at least one first latch for storing data based on a voltage level of a first sensing node; and a control circuit configured to adjust a level of a voltage signal provided to the page buffer circuit. The page buffer includes a trip control transistor arranged between the at least one first latch and the first sensing node, and wherein the control circuit is further configured to, based on a read operation being performed on the memory cell array, control a trip control voltage to be provided to a gate of the trip control transistor. A level of the trip control voltage varies according to a temperature of the memory device.
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