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公开(公告)号:US10509744B2
公开(公告)日:2019-12-17
申请号:US15844165
申请日:2017-12-15
发明人: Jeong Ho Lee , Sung Roh Yoon , Eui Young Chung , Jin Woo Kim , Young Jin Cho , Myeong Jin Kim , Sei Joon Kim , Jeong Bin Kim , Hyeok Jun Choe
摘要: A semiconductor system includes a CPU connected to a heterogeneous memory module via a system bus. The heterogeneous memory module includes; a volatile memory module, a nonvolatile memory module, an internal bus separate from the system bus and connecting the volatile memory module and the nonvolatile memory module, and a swap manager configured to control execution of a swap operation transferring target data between the volatile memory module and nonvolatile memory module using the internal bus and without using of the system bus.