公开(公告)号：US09537470B2

公开(公告)日：2017-01-03

申请号：US14824302

申请日：2015-08-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chung-Hee Kim ,  Min-Su Kim ,  Ji-Kyum Kim ,  Emil Kagramanyan ,  Dae-Seong Lee ,  Gun-Ok Jung ,  Uk-Rae Cho

IPC: H03K3/289 ,  H03K3/037

CPC classification number: H03K3/0372 ,  H03K3/0375

Abstract: Provided are a semiconductor device and a method for operating a semiconductor device. The semiconductor device includes a clock generating unit receiving a reference clock and generating first and second clocks that are different from each other from the reference clock; a first latch configured to receive input data based on the first clock and to output the input data as first output data; and a second latch configured to receive the first output data based on the second clock and to output the first output data as second output data, wherein a first edge of the first clock does not overlap a first edge of the second clock, and at least a part of a second edge of the first clock overlaps a second edge of the second clock.

Abstract translation: 提供半导体器件和用于操作半导体器件的方法。 所述半导体器件包括：时钟生成单元，接收参考时钟;产生与所述参考时钟不同的第一和第二时钟; 第一锁存器，被配置为基于所述第一时钟接收输入数据并将所述输入数据输出为第一输出数据; 以及第二锁存器，被配置为基于所述第二时钟接收所述第一输出数据并将所述第一输出数据输出为第二输出数据，其中所述第一时钟的第一边缘不与所述第二时钟的第一边缘重叠，并且至少 第一时钟的第二边缘的一部分与第二时钟的第二边缘重叠。

公开(公告)号：US10177166B2

公开(公告)日：2019-01-08

申请号：US15409674

申请日：2017-01-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju-Hyun Kang ,  Hyun Lee ,  Min-Su Kim ,  Ji-Kyum Kim ,  Jong-Woo Kim

IPC: H01L27/118 ,  G06F17/50

Abstract: An integrated circuit includes a complex logic cell. The complex logic cell includes a first logic circuit providing a first output signal from a first input signal group and a common input signal group, and a second logic circuit providing a second output signal from a second input signal group and the common input signal group. The first and second logic circuits respectively include first and second transistors formed from a gate electrode, the gate electrode extending in a first direction and receiving a first common input signal of the common input signal group.

公开(公告)号：US10586809B2

公开(公告)日：2020-03-10

申请号：US16211496

申请日：2018-12-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju-Hyun Kang ,  Hyun Lee ,  Min-Su Kim ,  Ji-Kyum Kim ,  Jong-Woo Kim

IPC: H01L27/118 ,  G06F17/50

Abstract: An integrated circuit includes a complex logic cell. The complex logic cell includes a first logic circuit providing a first output signal from a first input signal group and a common input signal group, and a second logic circuit providing a second output signal from a second input signal group and the common input signal group. The first and second logic circuits respectively include first and second transistors formed from a gate electrode, the gate electrode extending in a first direction and receiving a first common input signal of the common input signal group.

公开(公告)号：US09130550B2

公开(公告)日：2015-09-08

申请号：US14295802

申请日：2014-06-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chung-Hee Kim ,  Min-Su Kim ,  Ji-Kyum Kim ,  Emil Kagramanyan ,  Dae-Seong Lee ,  Gun-Ok Jung ,  Uk-Rae Cho

IPC: H03K3/289 ,  H03K3/037

CPC classification number: H03K3/0372 ,  H03K3/0375

Abstract: Provided are a semiconductor device and a method for operating a semiconductor device. The semiconductor device includes a clock generating unit receiving a reference clock and generating first and second clocks that are different from each other from the reference clock; a first latch configured to receive input data based on the first clock and to output the input data as first output data; and a second latch configured to receive the first output data based on the second clock and to output the first output data as second output data, wherein a first edge of the first clock does not overlap a first edge of the second clock, and at least a part of a second edge of the first clock overlaps a second edge of the second clock.

Abstract translation: 提供半导体器件和用于操作半导体器件的方法。 所述半导体器件包括：时钟生成单元，接收参考时钟;产生与所述参考时钟不同的第一和第二时钟; 第一锁存器，被配置为基于所述第一时钟接收输入数据并将所述输入数据输出为第一输出数据; 以及第二锁存器，被配置为基于所述第二时钟接收所述第一输出数据并将所述第一输出数据输出为第二输出数据，其中所述第一时钟的第一边缘不与所述第二时钟的第一边缘重叠，并且至少 第一时钟的第二边缘的一部分与第二时钟的第二边缘重叠。