公开(公告)号：US09318607B2

公开(公告)日：2016-04-19

申请号：US14273789

申请日：2014-05-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Woo Seo ,  Gun-Ok Jung ,  Min-Su Kim ,  Sang-Shin Han ,  Ju-Hyun Kang ,  Uk-Rae Cho

IPC: H01L23/528 ,  H01L27/02 ,  H01L29/78 ,  H01L23/538 ,  H01L27/092 ,  H01L27/12 ,  H01L27/06 ,  H01L23/00 ,  H01L25/10

CPC classification number: H01L29/785 ,  H01L23/5286 ,  H01L23/538 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L27/0207 ,  H01L27/0629 ,  H01L27/092 ,  H01L27/0924 ,  H01L27/1211 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/15331 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Provided are a semiconductor device and a method of fabricating the semiconductor device. The semiconductor device includes a first source electrode configured to connect a first power rail to a first impurity region, the first power rail coupled to a first voltage source, a second source electrode configured to connect a second power rail to a second impurity region, the second power rail coupled to a second voltage source, the first and second voltage sources being different, a gate electrode on the first and second impurity regions, a first drain electrode on the first impurity region, a second drain electrode on the second impurity region and an interconnection line connected to the first drain electrode and the second drain electrode, the interconnection line forming at least one closed loop.

Abstract translation: 提供半导体器件和制造半导体器件的方法。 半导体器件包括：第一源电极，被配置为将第一电力轨连接到第一杂质区，第一电源轨耦合到第一电压源;第二源极，被配置为将第二电力轨连接到第二杂质区; 第二电源轨耦合到第二电压源，第一和第二电压源不同，第一和第二杂质区上的栅电极，第一杂质区上的第一漏电极，第二杂质区上的第二漏电极， 连接到所述第一漏电极和所述第二漏极的互连线，所述互连线形成至少一个闭环。

公开(公告)号：US09130550B2

公开(公告)日：2015-09-08

申请号：US14295802

申请日：2014-06-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chung-Hee Kim ,  Min-Su Kim ,  Ji-Kyum Kim ,  Emil Kagramanyan ,  Dae-Seong Lee ,  Gun-Ok Jung ,  Uk-Rae Cho

IPC: H03K3/289 ,  H03K3/037

CPC classification number: H03K3/0372 ,  H03K3/0375

Abstract: Provided are a semiconductor device and a method for operating a semiconductor device. The semiconductor device includes a clock generating unit receiving a reference clock and generating first and second clocks that are different from each other from the reference clock; a first latch configured to receive input data based on the first clock and to output the input data as first output data; and a second latch configured to receive the first output data based on the second clock and to output the first output data as second output data, wherein a first edge of the first clock does not overlap a first edge of the second clock, and at least a part of a second edge of the first clock overlaps a second edge of the second clock.

Abstract translation: 提供半导体器件和用于操作半导体器件的方法。 所述半导体器件包括：时钟生成单元，接收参考时钟;产生与所述参考时钟不同的第一和第二时钟; 第一锁存器，被配置为基于所述第一时钟接收输入数据并将所述输入数据输出为第一输出数据; 以及第二锁存器，被配置为基于所述第二时钟接收所述第一输出数据并将所述第一输出数据输出为第二输出数据，其中所述第一时钟的第一边缘不与所述第二时钟的第一边缘重叠，并且至少 第一时钟的第二边缘的一部分与第二时钟的第二边缘重叠。

公开(公告)号：US09537470B2

公开(公告)日：2017-01-03

申请号：US14824302

申请日：2015-08-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chung-Hee Kim ,  Min-Su Kim ,  Ji-Kyum Kim ,  Emil Kagramanyan ,  Dae-Seong Lee ,  Gun-Ok Jung ,  Uk-Rae Cho

IPC: H03K3/289 ,  H03K3/037

CPC classification number: H03K3/0372 ,  H03K3/0375

Abstract: Provided are a semiconductor device and a method for operating a semiconductor device. The semiconductor device includes a clock generating unit receiving a reference clock and generating first and second clocks that are different from each other from the reference clock; a first latch configured to receive input data based on the first clock and to output the input data as first output data; and a second latch configured to receive the first output data based on the second clock and to output the first output data as second output data, wherein a first edge of the first clock does not overlap a first edge of the second clock, and at least a part of a second edge of the first clock overlaps a second edge of the second clock.

Abstract translation: 提供半导体器件和用于操作半导体器件的方法。 所述半导体器件包括：时钟生成单元，接收参考时钟;产生与所述参考时钟不同的第一和第二时钟; 第一锁存器，被配置为基于所述第一时钟接收输入数据并将所述输入数据输出为第一输出数据; 以及第二锁存器，被配置为基于所述第二时钟接收所述第一输出数据并将所述第一输出数据输出为第二输出数据，其中所述第一时钟的第一边缘不与所述第二时钟的第一边缘重叠，并且至少 第一时钟的第二边缘的一部分与第二时钟的第二边缘重叠。