公开(公告)号：US10075153B2

公开(公告)日：2018-09-11

申请号：US15390813

申请日：2016-12-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taek Kyun Shin ,  Jin Pyo Park ,  Soong Hyun Shin ,  Jung Hun Heo

IPC: H04L7/00 ,  H03K5/135 ,  H03K5/14 ,  H04L7/033 ,  H03K5/00

CPC classification number: H03K5/135 ,  H03K5/14 ,  H03K2005/00078 ,  H04L7/0331

Abstract: A low-power synchronizer circuit, a data processing circuit that incorporates the synchronizer circuit, and a synchronization method are provided. The synchronizer circuit includes a delay circuit for receiving and delaying an asynchronous input signal, a first flip-flop having an input terminal connected to an output terminal of the delay circuit, a clock terminal for receiving the asynchronous input signal, and a reset terminal for receiving the asynchronous input signal, a synchronizer connected to an output terminal of the first flip-flop, and a clock-gating circuit for receiving a clock signal and determining whether to supply the clock signal to the synchronizer in response to one of a first output value of the delay circuit and a second output value of the first flip-flop and a third output value of the synchronizer.