公开(公告)号：US20240196587A1

公开(公告)日：2024-06-13

申请号：US18229762

申请日：2023-08-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinseo CHOI ,  Sohyang LEE ,  Jeongmin JIN ,  Sohee CHOI

IPC: H10B12/00

CPC classification number: H10B12/02 ,  H10B12/315 ,  H10B12/482

Abstract: A method of fabricating a semiconductor device include providing a substrate including cell and peripheral regions, forming a cell gate structure on the cell region, forming a peripheral gate structure on the peripheral region, forming a bit-line structure on the cell region, forming a preliminary pad layer covering the bit-line structure and the peripheral gate structure, and etching the preliminary pad layer to form a landing pad and a peripheral conductive pad. The etching the preliminary pad layer includes forming a first mask structure on the preliminary pad layer, forming a second mask structure on the first mask structure, forming a first photoresist layer on the second mask structure, and using the first photoresist layer as an etching mask to etch the second mask structure. The first photoresist layer includes a first line opening overlapping the cell region, and peripheral resist patterns overlapping the peripheral region.

公开(公告)号：US20220122986A1

公开(公告)日：2022-04-21

申请号：US17398136

申请日：2021-08-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sukhwa JANG ,  Kanguk KIM ,  Hyunsuk NOH ,  Yeongshin PARK ,  Sangkyu SUN ,  Sunyoung LEE ,  Sohyang LEE ,  Hongjun LEE ,  Hosun JUNG ,  Jeongmin JIN ,  Jeonghee CHOI ,  Jinseo CHOI ,  Cera HONG

IPC: H01L27/108

Abstract: A method of manufacturing a semiconductor device includes forming a lower structure including a plurality of transistors, forming a conductive layer on the lower structure, forming first preliminary pad mask patterns and wiring mask patterns on the conductive layer, forming pad mask patterns by patterning the first preliminary pad mask patterns while protecting the wiring mask patterns, and etching the conductive layer using the pad mask patterns and the wiring mask patterns as an etching mask to form pad patterns and wiring patterns.