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1.发明申请公开(公告)号：US20230035456A1
公开(公告)日：2023-02-02
申请号：US17719622
申请日：2022-04-13
发明人： Hyunchul LEE , Kijeong KIM , Jongcheon KIM , Donghwi SHIN , Hyunsil HONG
IPC分类号： H01L27/108 , H01L21/027 , H01L21/311
摘要： In a method of forming a wiring, an insulating interlayer including a low-k dielectric material is formed on a substrate. A first etching mask is formed on the insulating interlayer. A first etching process is performed using the first etching mask to form a first opening through the insulating interlayer. The first etching mask is removed. A protection pattern is formed on a bottom and a side of the first opening. A second etching mask is formed on the protection pattern and the insulating interlayer. A second etching process is performed using a second etching mask to form a second opening through the insulating interlayer. The second etching mask is removed. The protection pattern is removed. A wiring is formed in each of the first and second openings.
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公开(公告)号：US20230069868A1
公开(公告)日：2023-03-09
申请号：US17698476
申请日：2022-03-18
发明人： Jongcheon KIM , Hyunchul LEE , Ki-Jeong KIM , Donghwi SHIN , Hyun-Sil HONG
IPC分类号： H01L21/311 , H01L21/768 , H01L21/027 , H01L23/522 , H01L23/528
摘要： A method of fabricating a semiconductor device and a device fabricated thereby, the method including sequentially stacking an interlayer insulating layer, a porous dielectric layer, a first mask layer, and a second mask layer on a substrate; etching the second mask layer to form preliminary mask patterns; etching the preliminary mask patterns to form second mask patterns; etching the first mask layer using the second mask patterns as an etch mask to form first mask patterns; etching the porous dielectric layer using the first mask patterns as an etch mask to form grooves; and forming interconnection patterns in the grooves, respectively, wherein the porous dielectric layer includes SiOCH, and the first mask layer includes carbon-free silicon oxide (SiO2).
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