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公开(公告)号:US20230069868A1
公开(公告)日:2023-03-09
申请号:US17698476
申请日:2022-03-18
发明人: Jongcheon KIM , Hyunchul LEE , Ki-Jeong KIM , Donghwi SHIN , Hyun-Sil HONG
IPC分类号: H01L21/311 , H01L21/768 , H01L21/027 , H01L23/522 , H01L23/528
摘要: A method of fabricating a semiconductor device and a device fabricated thereby, the method including sequentially stacking an interlayer insulating layer, a porous dielectric layer, a first mask layer, and a second mask layer on a substrate; etching the second mask layer to form preliminary mask patterns; etching the preliminary mask patterns to form second mask patterns; etching the first mask layer using the second mask patterns as an etch mask to form first mask patterns; etching the porous dielectric layer using the first mask patterns as an etch mask to form grooves; and forming interconnection patterns in the grooves, respectively, wherein the porous dielectric layer includes SiOCH, and the first mask layer includes carbon-free silicon oxide (SiO2).
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公开(公告)号:US20230013061A1
公开(公告)日:2023-01-19
申请号:US17668452
申请日:2022-02-10
发明人: Hyunchul LEE , Ki-Jeong KIM , Hwan LIM , Hyun-Sil HONG
IPC分类号: H01L21/762 , H01L29/423 , H01L21/02 , H01L27/108
摘要: A semiconductor device includes a substrate having one or more inner surfaces defining trenches that define an active pattern of the substrate, the trenches including a first trench and a second trench which have different widths, a device isolation layer on the substrate such that the device isolation layer at least partially fills the trenches, and a word line intersecting the active pattern. The device isolation layer includes a first isolation pattern covering a portion of the second trench, a second isolation pattern on the first isolation pattern and covering a remaining portion of the second trench, and a filling pattern filling the first trench under the word line. A top surface of the second isolation pattern is located at a higher level than a top surface of the filling pattern.
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