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    INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME
    1.
    发明申请
    INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME 有权

    公开(公告)号：US20210005548A1

    公开(公告)日：2021-01-07

    申请号：US16742233

    申请日：2020-01-14

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Woojin LEE ,  Junghoo SHIN ,  Sanghoon AHN ,  Junhyuk LIM ,  Daehan KIM

    IPC: H01L23/522 ,  H01L23/528 ,  H01L21/768

    Abstract: An integrated circuit device includes a first insulation layer on a substrate, a lower wiring structure in the first insulation layer and including a metal layer and a conductive barrier layer, such that the metal layer is on the conductive barrier layer, an etch stop layer overlapping an upper surface of the first insulation layer and an upper surface of the conductive barrier layer and having a first thickness, a capping layer overlapping a portion of the upper surface of the metal layer and having a second thickness which is less than the first thickness, a second insulation layer overlapping the etch stop layer and the capping layer, and an upper wiring structure connected to another portion of the upper surface of the metal layer not overlapped by the capping layer in the second insulation layer.

    SEMICONDUCTOR DEVICE
    2.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20230027640A1

    公开(公告)日：2023-01-26

    申请号：US17699496

    申请日：2022-03-21

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jongmin BAEK ,  Junghoo SHIN ,  Sangshin JANG ,  Junghwan CHUN ,  Kyeongbeom PARK ,  Suhyun BARK

    IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768

    Abstract: A semiconductor device includes a substrate having an active region, a first insulating layer on the substrate, a second insulating layer on the first insulating layer, an etch stop layer between the first insulating layer and the second insulating layer, a via contact in the first insulating layer and electrically connected to the active region, an interconnection electrode in the second insulating layer and electrically connected to the via contact, a conductive barrier layer on a side surface and a lower surface of the interconnection electrode and having an extension portion extending to a partial region of a side surface of the via contact, and a side insulating layer on a side region of the via contact below the extension portion of the conductive barrier layer, the side insulating layer including the same material as a material of the etch stop layer.

    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE SUPPRESSING LEAKAGE CURRENT OF MULTILAYER WIRING STRUCTURES
    4.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE SUPPRESSING LEAKAGE CURRENT OF MULTILAYER WIRING STRUCTURES 有权

    公开(公告)号：US20250014998A1

    公开(公告)日：2025-01-09

    申请号：US18897275

    申请日：2024-09-26

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Junghoo SHIN ,  Jongmin Baek ,  Sanghoon Ahn ,  Woojin Lee ,  Junhyuk Lim

    IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

    Abstract: A semiconductor integrated circuit device includes a substrate; a transistor on the substrate; an interlayer insulating film on the transistor; an insulating liner on the interlayer insulating film; a first insulating film on the insulating liner; and a first wiring layer on the interlayer insulating film and surrounded by the insulating liner. A height of a top surface of the first insulating film in a vertical direction from a main surface of the interlayer insulating film is different than a height of a top surface of the first wiring layer in the vertical direction. A step exists between the top surfaces of the first wiring layer and the first insulating film. A height of the first insulating film is greater than a height of the first wiring layer. A width of the first wiring layer gradually narrows as the first wiring layer extends upwards along the vertical direction.

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