公开(公告)号：US20240304622A1

公开(公告)日：2024-09-12

申请号：US18416403

申请日：2024-01-18

Applicant: Samsung Electronics Co., Ltd. ,  THE UNIVERSITY OF CHICAGO

Inventor： Minsu SEOL ,  Ce LIANG ,  Jiwoong PARK ,  Kyung-Eun BYUN ,  Changhyun KIM

IPC: H01L27/092 ,  H01L21/02 ,  H01L21/8256 ,  H01L29/24 ,  H01L29/66 ,  H01L29/76

CPC classification number: H01L27/092 ,  H01L21/02568 ,  H01L21/8256 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/7606

Abstract: Provided are a semiconductor device including a two-dimensional material and a method of manufacturing the semiconductor device. The semiconductor device may include a substrate, first and second two-dimensional material layers on the substrate and junctioned to each other in a lateral direction to form a coherent interface, a first source electrode and a first drain electrode on the first two-dimensional material layer, a first gate electrode between the first source electrode and the first drain electrode, a second source electrode and a second drain electrode on the second two-dimensional material layer, and a second gate electrode between the second source electrode and the second drain electrode.

公开(公告)号：US20240234583A1

公开(公告)日：2024-07-11

申请号：US18397325

申请日：2023-12-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junyoung KWON ,  Kyung-Eun BYUN ,  Minsu SEOL

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775

CPC classification number: H01L29/78696 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/7869

Abstract: Provided are a semiconductor device including a two-dimensional (2D) material and an electronic device including the semiconductor device. The semiconductor device may include a channel layer including a two-dimensional (2D) semiconductor material, a channel portion, and an extension portion on both sides of the channel portion, a source electrode and a drain electrode respectively on both sides of the channel layer, a gate electrode surrounding the channel portion, a first insulating layer between the channel portion of the channel layer and the gate electrode, and a second insulating layer on the extension portion of the channel layer. The second insulating layer may include a different material than a material of the first insulating layer. The second insulating layer may include a n-type dopant or p-type dopant. A dopant in the extension portion may be the same as a dopant in the second insulating layer.

公开(公告)号：US20240222524A1

公开(公告)日：2024-07-04

申请号：US18507905

申请日：2023-11-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minsu SEOL ,  Eunkyu LEE ,  Junyoung KWON ,  Kyung-Eun BYUN

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/78696 ,  H01L29/0603 ,  H01L29/66795 ,  H01L29/785

Abstract: Provided are a field effect transistor, a method of manufacturing the field effect transistor, and an electronic device and an electronic apparatus each including the field effect transistor. The field effect transistor includes a channel layer disposed on a substrate, a high-k gate insulating layer disposed on the channel layer, a first composite electrode layer connected to a first side of the channel layer, a second composite electrode layer connected to a second side of the channel layer, and a gate electrode layer disposed on the gate insulating layer. At least one of the first and second composite electrode layers includes a contact resistance reducing layer in contact with the channel layer and a conductive layer in contact with the contact resistance reducing layer. The conductive layer is spaced apart from the channel layer.

公开(公告)号：US20240178307A1

公开(公告)日：2024-05-30

申请号：US18518729

申请日：2023-11-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minsu SEOL ,  Sungil PARK ,  Jaehyun PARK ,  Kyung-Eun BYUN ,  Eunkyu LEE ,  Junyoung KWON ,  Minseok YOO

IPC: H01L29/76 ,  H01L29/24 ,  H01L29/78

CPC classification number: H01L29/7606 ,  H01L29/24 ,  H01L29/78391

Abstract: A semiconductor device may include a multi-layer gate dielectric layer and an electronic apparatus including the semiconductor device. The semiconductor device may include a channel layer including a two-dimensional semiconductor material, a gate dielectric layer on a first area of the channel layer, a gate electrode on the gate dielectric layer, and source and drain electrodes in a second area of the channel layer. The gate dielectric layer may include a high-k dielectric layer and an intermediate dielectric layer. The intermediate dielectric layer may be between the high-k dielectric layer and the channel layer. A dielectric constant of the intermediate dielectric layer may be less than a dielectric constant of the high-k dielectric layer.

公开(公告)号：US20230123234A1

公开(公告)日：2023-04-20

申请号：US17703201

申请日：2022-03-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keunwook SHIN ,  Kyung-Eun BYUN ,  Sangsoo LEE ,  Changhyun KIM ,  Changseok LEE

IPC: H01L29/786 ,  H01L29/16 ,  H01L27/11597 ,  H01L27/11582

Abstract: Provided is a thin film structure including a substrate, a metal layer on the substrate and spaced apart from the substrate, and a two-dimensional material layer between the substrate and the metal layer. The two-dimensional material layer may be configured to limit and/or block an electron transfer between the substrate and the metal layer. A resistivity of a metal layer on the two-dimensional material layer may be lowered by the two-dimensional material layer.

公开(公告)号：US20230081960A1

公开(公告)日：2023-03-16

申请号：US17697400

申请日：2022-03-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung-Eun BYUN ,  Sangwon KIM ,  Changhyun KIM ,  Keunwook SHIN ,  Changseok LEE

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/417 ,  H01L29/10 ,  H01L29/423

Abstract: A vertical channel transistor includes a first source/drain electrode; a second source/drain electrode spaced apart from the first source/drain electrode in a first direction; a first channel pattern between the first source/drain electrode and the second source/drain electrode; a first gate electrode on a side surface of the first channel pattern; a first gate insulation layer between the first channel pattern and the first gate electrode; and a first graphene insertion layer between the first source/drain electrode and the first channel pattern.

公开(公告)号：US20230041352A1

公开(公告)日：2023-02-09

申请号：US17565807

申请日：2021-12-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keunwook SHIN ,  Seunggeol NAM ,  Kyung-Eun BYUN ,  Hyeonjin SHIN

IPC: H01L23/528 ,  H01L23/532

Abstract: Provided are an interconnect structure and an electronic device including the interconnect structure. The interconnect structure may include a dielectric layer including a trench; a conductive line in the trench; and a first cap layer on an upper surface of the conductive line. The first cap layer may include a graphene-metal composite including graphene and a metal mixed with each other.

公开(公告)号：US20220085025A1

公开(公告)日：2022-03-17

申请号：US17225601

申请日：2021-04-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunseok LIM ,  Minhyuk CHO ,  Kyung-Eun BYUN ,  Hyeonjin SHIN ,  Kaoru YAMAMOTO ,  Jungsoo YOON ,  Soyoung LEE ,  Geuno JEONG

IPC: H01L27/108

Abstract: A wiring structure includes a first conductive pattern including doped polysilicon on a substrate, an ohmic contact pattern including a metal silicide on the first conductive pattern, an oxidation prevention pattern including a metal silicon nitride on the ohmic contact pattern, a diffusion barrier including graphene on the oxidation prevention pattern, and a second conductive pattern including a metal on the diffusion barrier.

公开(公告)号：US20210276873A1

公开(公告)日：2021-09-09

申请号：US17190852

申请日：2021-03-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangwon KIM ,  Kyung-Eun BYUN ,  Hyeonjin SHIN ,  Eunkyu LEE ,  Changseok LEE

IPC: C01B32/186

Abstract: A graphene manufacturing apparatus includes a reaction chamber a substrate supporter configured to structurally support a substrate inside the reaction chamber; a plasma generator configured to generate a plasma inside the reaction chamber; a first gas supply configured to supply an inert gas into the reaction chamber at a first height from an upper surface of the substrate supporter in a height direction of the reaction chamber; a second gas supply configured to supply a carbon source into the reaction chamber at a second height from the upper surface of the substrate supporter in the height direction of the reaction chamber; and a third gas supply configured to supply a reducing gas into the reaction chamber, wherein the first to third gas supply units are disposed at different heights at a third height from the upper surface of the substrate supporter in the height direction of the reaction chamber.

公开(公告)号：US20210020438A1

公开(公告)日：2021-01-21

申请号：US16928560

申请日：2020-07-14

Applicant: Samsung Electronics Co., Ltd. ,  RESEARCH & BUSINESS FOUNDATION SUNGKYUNKWAN UNIVERSITY

Inventor： Kyung-Eun BYUN ,  Hyoungsub KIM ,  Taejin PARK ,  Hoijoon KIM ,  Hyeonjin SHIN ,  Wonsik AHN ,  Mirine LEEM ,  Yeonchoo CHO

IPC: H01L21/02

Abstract: A method of forming a transition metal dichalcogenide thin film on a substrate includes treating the substrate with a metal organic material and providing a transition metal precursor and a chalcogen precursor around the substrate to synthesize transition metal dichalcogenide on the substrate. The transition metal precursor may include a transition metal element and the chalcogen precursor may include a chalcogen element.