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    SEMICONDUCTOR DEVICES
    1.
    发明公开
    SEMICONDUCTOR DEVICES 审中-公开

    公开(公告)号：US20240258204A1

    公开(公告)日：2024-08-01

    申请号：US18486853

    申请日：2023-10-13

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Yeonggil KIM ,  Hoonseok SEO ,  Minchul AHN ,  Wookyung YOU ,  Woojin LEE ,  Junghwan CHUN

    IPC: H01L23/48 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

    CPC classification number: H01L23/481 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

    Abstract: A semiconductor device comprising: a substrate including an active region extending in a first direction; a gate structure extending in a second direction on the active region; source/drain regions on the active region and adjacent the gate structure; a backside insulating layer on a lower surface of the substrate; a vertical power structure between adjacent source/drain regions, wherein the vertical power structure extends through the substrate and the backside insulating layer and has an exposed lower surface exposed; an interlayer insulating layer on the backside insulating layer; a backside power structure that extends through the interlayer insulating layer and is connected to the vertical power structure; and a first alignment insulating layer between the backside insulating layer and the interlayer insulating layer, wherein the first alignment insulating layer has a first opening exposing the lower surface of the vertical power structure and contacts the backside power structure.

    SEMICONDUCTOR DEVICES HAVING GATE ISOLATION LAYERS
    3.
    发明申请
    SEMICONDUCTOR DEVICES HAVING GATE ISOLATION LAYERS 有权

    公开(公告)号：US20220254880A1

    公开(公告)日：2022-08-11

    申请号：US17400358

    申请日：2021-08-12

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Seonbae KIM ,  Woojin LEE ,  Seunghoon CHOI

    IPC: H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78

    Abstract: A semiconductor device includes active regions on a substrate, a gate structure intersecting the active regions, a source/drain region on the active regions and at a side surface of the gate structure, a gate spacer between the gate structure and the source/drain region, the gate spacer contacting the side surface of the gate structure, a lower source/drain contact plug connected to the source/drain region, a gate isolation layer on the gate spacer, an upper end of the gate isolation layer being at a higher level than an upper surface of the gate structure and an upper surface of the lower source/drain contact plug, a capping layer covering the gate structure, the lower source/drain contact plug, and the gate isolation layer, and an upper source/drain contact plug connected to the lower source/drain contact plug and extending through the capping layer.

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    4.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开

    公开(公告)号：US20200098620A1

    公开(公告)日：2020-03-26

    申请号：US16411439

    申请日：2019-05-14

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Woojin LEE ,  Hoon Seok SEO ,  Sanghoon AHN ,  Kyu-Hee HAN

    IPC: H01L21/768 ,  H01L21/311

    Abstract: A semiconductor device includes a substrate including an active pattern, a first interlayer dielectric layer on the substrate, the first interlayer dielectric layer including a recess on an upper portion thereof, and a lower connection line in the first interlayer dielectric layer, the lower connection line being electrically connected to the active pattern, and the lower connection line including a conductive pattern, the recess of the first interlayer dielectric layer selectively exposing a top surface of the conductive pattern, and a barrier pattern between the conductive pattern and the first interlayer dielectric layer, the first interlayer dielectric layer covering a top surface of the barrier pattern.

    ELECTRICAL CONDUCTORS, PRODUCTION METHODS THEREOF, AND ELECTRONIC DEVICES INCLUDING THE SAME
    7.
    发明申请
    ELECTRICAL CONDUCTORS, PRODUCTION METHODS THEREOF, AND ELECTRONIC DEVICES INCLUDING THE SAME 有权
    电导体及其制造方法以及包括其的电子器件

    公开(公告)号：US20170064822A1

    公开(公告)日：2017-03-02

    申请号：US15235363

    申请日：2016-08-12

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Doh Won JUNG ,  Yoon Chul SON ,  Woojin LEE ,  Jongmin LEE

    IPC: H05K1/09 ,  H05K3/22

    CPC classification number: H05K1/09 ,  H05K1/028 ,  H05K1/0393 ,  H05K3/22 ,  H05K3/24 ,  H05K2201/0326 ,  H05K2201/0338 ,  H05K2203/0108 ,  H05K2203/0257 ,  H05K2203/1105

    Abstract: An electrical conductor includes a first conductive layer including a plurality of metal oxide nanosheets, wherein a metal oxide nanosheet of the plurality of metal oxide nanosheets includes a proton bonded to a the surface of the metal oxide nanosheet, wherein the metal oxide is represented by Chemical Formula 1: MO2   Chemical Formula 1 wherein M is Re, V, Os, Ru, Ta, Ir, Nb, W, Ga, Mo, In, Cr, Rh, or Mn, wherein the plurality of metal oxide nanosheets has a content of hydrogen atoms of less than about 100 atomic percent, with respect to 100 atomic percent of metal atoms as measured by Rutherford backscattering spectrometry, and wherein the plurality of metal oxide nanosheets includes an electrical connection between contacting metal oxide nanosheets.

    Abstract translation: 其中M是Re，V，Os，Ru，Ta，Ir，Nb，W，Ga，Mo，In，Cr，Rh或Mn，其中多个金属氧化物纳米片的氢原子含量小于约100 原子百分比，相对于通过卢瑟福背散射光谱法测量的100原子％的金属原子，并且其中多个金属氧化物纳米片包括在接触金属氧化物纳米片之间的电连接。

    SEMICONDUCTOR DEVICES HAVING GATE ISOLATION LAYERS
    10.
    发明公开
    SEMICONDUCTOR DEVICES HAVING GATE ISOLATION LAYERS 审中-公开

    公开(公告)号：US20230290818A1

    公开(公告)日：2023-09-14

    申请号：US18200638

    申请日：2023-05-23

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Seonbae KIM ,  Woojin LEE ,  Seunghoon CHOI

    IPC: H01L29/06 ,  H01L29/78 ,  H01L29/423 ,  H01L29/417

    CPC classification number: H01L29/0649 ,  H01L29/785 ,  H01L29/42364 ,  H01L29/41791

    Abstract: A semiconductor device includes active regions on a substrate, a gate structure intersecting the active regions, a source/drain region on the active regions and at a side surface of the gate structure, a gate spacer between the gate structure and the source/drain region, the gate spacer contacting the side surface of the gate structure, a lower source/drain contact plug connected to the source/drain region, a gate isolation layer on the gate spacer, an upper end of the gate isolation layer being at a higher level than an upper surface of the gate structure and an upper surface of the lower source/drain contact plug, a capping layer covering the gate structure, the lower source/drain contact plug, and the gate isolation layer, and an upper source/drain contact plug connected to the lower source/drain contact plug and extending through the capping layer.

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