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公开(公告)号:US12033997B2
公开(公告)日:2024-07-09
申请号:US17035619
申请日:2020-09-28
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jungkyu Chae
IPC: H01L27/02 , H01L23/522 , H01L23/528
CPC classification number: H01L27/0207 , H01L23/5226 , H01L23/5286
Abstract: A standard cell comprises a first active region and a first power rail, the first active region and the first power rail disposed in a first MOS region; a second active region and a second power rail, the second active region and the second power rail disposed in a second MOS region; and a gate electrode extending to cross the first and second active regions and the first and second power rails in a first direction, wherein the first power rail is disposed closer to a boundary between the first MOS region and the second MOS region than to a first side of the first MOS region opposite the boundary, and wherein the second power rail is disposed closer to the boundary between the first MOS region and the second MOS region than to a first side of the second MOS region opposite the boundary.
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公开(公告)号:US11640959B2
公开(公告)日:2023-05-02
申请号:US16931585
申请日:2020-07-17
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Jungkyu Chae , Kwanyoung Chun , Yoonjin Kim
Abstract: A semiconductor device includes a pair of first and second dummy active regions extending in a first horizontal direction and spaced apart from each other in a second horizontal direction; a pair of first and second circuit active regions extending in the first horizontal direction and spaced apart in the second horizontal direction; and a plurality of line patterns extending in the second horizontal direction and spaced apart in the first horizontal direction. The pair of first and second dummy active regions may be between a pair of line patterns adjacent to each other among the plurality of line patterns. At least one of the first and second dummy active regions may have a width-changing portion in which a width of the at least one of the first and second dummy active regions changes in the second horizontal direction between the pair of line patterns adjacent to each other.
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公开(公告)号:US12261166B2
公开(公告)日:2025-03-25
申请号:US18140115
申请日:2023-04-27
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Jungkyu Chae , Kwanyoung Chun , Yoonjin Kim
IPC: H01L27/02
Abstract: A semiconductor device includes a pair of first and second dummy active regions extending in a first horizontal direction and spaced apart from each other in a second horizontal direction; a pair of first and second circuit active regions extending in the first horizontal direction and spaced apart in the second horizontal direction; and a plurality of line patterns extending in the second horizontal direction and spaced apart in the first horizontal direction. The pair of first and second dummy active regions may be between a pair of line patterns adjacent to each other among the plurality of line patterns. At least one of the first and second dummy active regions may have a width-changing portion in which a width of the at least one of the first and second dummy active regions changes in the second horizontal direction between the pair of line patterns adjacent to each other.
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公开(公告)号:US11222158B2
公开(公告)日:2022-01-11
申请号:US17034634
申请日:2020-09-28
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jungkyu Chae , Jinwoo Jeong , Kwanyoung Chun
IPC: G06F30/392 , G06F30/3312 , H01L29/06 , G06F119/12 , H01L29/786 , G06F119/18 , H01L29/423
Abstract: A method of manufacturing an integrated circuit includes: generating layout data of the integrated circuit by placing and routing standard cells that define the integrated circuit, the standard cells including a nanosheet; generating timing analysis data by performing a timing analysis of the integrated circuit using the layout data; and regenerating the layout data of the integrated circuit by replacing and rerouting the standard cells that define the integrated circuit based on the timing analysis data and a shape of the nanosheet of the placed standard cells.
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