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    Integrated circuits and semiconductor device including standard cell
    2.
    发明授权
    Integrated circuits and semiconductor device including standard cell 有权

    公开(公告)号：US10943923B2

    公开(公告)日：2021-03-09

    申请号：US16574339

    申请日：2019-09-18

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jinwoo Jeong ,  Jiwook Kwon ,  Sutae Kim ,  Hyelim Kim

    IPC: H01L27/118 ,  H01L27/02

    Abstract: A semiconductor device including first and second active regions extending in a first direction; a field region between the first and second active regions; a gate structure including an upper gate electrode overlapping the first active region and extending in a second direction crossing the first direction, and a lower gate electrode overlapping the second active region, extending in the second direction, and on a same line as the upper gate electrode; a gate isolation layer between the upper and lower gate electrodes; source/drain regions on respective sides of the upper gate electrode; a contact jumper crossing the upper gate electrode in the first active region and electrically connecting the source/drain regions; and a first upper contact extending in the second direction in the field region and overlapping the lower gate electrode and the gate isolation layer, wherein the upper gate electrode is a dummy gate electrode.

    Semiconductor integrated circuit
    3.
    发明授权
    Semiconductor integrated circuit 有权

    公开(公告)号：US11631672B2

    公开(公告)日：2023-04-18

    申请号：US16997335

    申请日：2020-08-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jinwoo Jeong ,  Raheel Azmat

    IPC: H01L27/092 ,  H01L27/02

    Abstract: A semiconductor integrated circuit includes a substrate, and a standard cell on the substrate. The standard cell includes a first wiring structure electrically connecting a first gate pattern to a fourth gate pattern, and a second wiring structure electrically connecting a second gate pattern to a third gate pattern. The first wiring structure includes a first lower wiring layer, a second lower wiring layer, first and second intermediate wiring layers, and a first upper wiring layer. The second wiring structure includes a third lower wiring layer, a fourth lower wiring layer, third and fourth intermediate wiring layers, and a second upper wiring layer.

    Semiconductor device
    4.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US11348918B2

    公开(公告)日：2022-05-31

    申请号：US16864260

    申请日：2020-05-01

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Taehyung Kim ,  Jinwoo Jeong ,  Jiwook Kwon ,  Raheel Azmat ,  Kwanyoung Chun

    IPC: H01L27/092 ,  H01L23/528 ,  H01L27/11 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66 ,  H01L27/02

    Abstract: A semiconductor device including a substrate; first to third active patterns on an upper portion of the substrate, the active patterns being sequentially arranged in a first direction and extending in a second direction crossing the first direction; first to third power rails respectively connected to the first to third active patterns, wherein a width of the second active pattern in the first direction is at least two times a width of the first active pattern in the first direction and is at least two times a width of the third active pattern in the first direction, the first active pattern is not vertically overlapped with the first power rail, the second active pattern is vertically overlapped with the second power rail, and the third active pattern is not vertically overlapped with the third power rail.

    Semiconductor device
    5.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US11322616B2

    公开(公告)日：2022-05-03

    申请号：US16781991

    申请日：2020-02-04

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jinwoo Jeong ,  Jaehyoung Lim

    IPC: H01L29/78 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/12 ,  H01L29/06 ,  H01L29/66

    Abstract: A semiconductor device includes a substrate that includes a first active region and a second active region, a device isolation layer between the first active region and the second active region, a gate structure that extends in a first direction and runs across the first active region and the second active region, a first active contact pattern on the first active region on one side of the gate structure, a second active contact pattern on the second active region on another side of the gate structure, and a connection pattern that is on the device isolation layer and connects the first active contact pattern and the second active contact pattern to each other. The connection pattern extends in a second direction and runs across the gate structure. Portions of the first active contact pattern and the second active contact pattern extend in the first direction and overlap the device isolation layer.

    Scan flip-flop, flip-flop and scan test circuit including the same
    6.
    发明授权
    Scan flip-flop, flip-flop and scan test circuit including the same 有权

    公开(公告)号：US11223344B2

    公开(公告)日：2022-01-11

    申请号：US16993946

    申请日：2020-08-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Raheel Azmat ,  Jaehyoung Lim ,  Taehyung Kim ,  Jinwoo Jeong ,  Jaeseok Yang

    IPC: H03K3/037 ,  G01R31/317 ,  G01R31/3177

    Abstract: A scan flip-flop includes a multiplexer, a first latch, a second latch, an output buffer and a clock buffer. The multiplexer selects one of a data input signal and a scan input signal based on an operation mode. The first latch latches an output of the multiplexer. The second latch latches an output of the first latch. The output buffer generates an output signal based on an output of the second latch. The clock buffer generates a first clock signal and a second clock signal that control operation of the first latch and the second latch. The first latch, the second latch, and the clock buffer are sequentially arranged along a first direction. A first clock line supplying the first clock signal and a second clock line supplying the second clock signal have a cross couple connection.

    SCAN FLIP-FLOP, FLIP-FLOP AND SCAN TEST CIRCUIT INCLUDING THE SAME
    9.
    发明申请
    SCAN FLIP-FLOP, FLIP-FLOP AND SCAN TEST CIRCUIT INCLUDING THE SAME 有权

    公开(公告)号：US20210152162A1

    公开(公告)日：2021-05-20

    申请号：US16993946

    申请日：2020-08-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Raheel Azmat ,  Jaehyoung Lim ,  Taehyung Kim ,  Jinwoo Jeong ,  Jaeseok Yang

    IPC: H03K3/037 ,  G01R31/3177 ,  G01R31/317

    Abstract: A scan flip-flop includes a multiplexer, a first latch, a second latch, an output buffer and a clock buffer. The multiplexer selects one of a data input signal and a scan input signal based on an operation mode. The first latch latches an output of the multiplexer. The second latch latches an output of the first latch. The output buffer generates an output signal based on an output of the second latch. The clock buffer generates a first clock signal and a second clock signal that control operation of the first latch and the second latch. The first latch, the second latch, and the clock buffer are sequentially arranged along a first direction. Each of the multiplexer and the output buffer is adjacent the first latch, the second latch, or the clock buffer along a second direction intersecting the first direction. A first clock line supplying the first clock signal and a second clock line supplying the second clock signal have a cross couple connection.

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