公开(公告)号：US11632228B2

公开(公告)日：2023-04-18

申请号：US17476782

申请日：2021-09-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jungpil Lim ,  Kyungho Ryu ,  Kilhoon Lee ,  Hyunwook Lim

IPC: H04L7/00 ,  H03L7/10 ,  H03L7/099 ,  H03L7/089 ,  H03L7/113

Abstract: A display device including: a timing controller outputting a reference clock signal and a data packet, wherein the data packet includes a clock signal embedded in a data signal; a clock and data recovery (CDR) circuit receiving the reference clock signal and the data packet; and a display panel displaying an image based on the data packet, wherein, when the CDR circuit receives the reference clock signal, a frequency band of the reference clock signal is detected using a first internal clock signal, a parameter associated with jitter characteristics of the clock and data recovery circuit is adjusted according to the detected frequency band, and a second internal clock signal is output by adjusting a frequency of the first internal clock signal, and when the CDR circuit receives the data packet, the data signal and a clock signal synchronized with the data signal are recovered from the data packet.

公开(公告)号：US11133920B2

公开(公告)日：2021-09-28

申请号：US16878728

申请日：2020-05-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jungpil Lim ,  Kyungho Ryu ,  Kilhoon Lee ,  Hyunwook Lim

IPC: H04L7/00 ,  H03L7/10

Abstract: A display device including: a timing controller outputting a reference clock signal and a data packet, wherein the data, packet includes a clock signal embedded in a data signal; a clock and data recovery (CDR) circuit receiving the reference clock signal and the data packet; and a display panel displaying an image based on the data packet, wherein, when the CDR circuit receives the reference clock signal, a frequency band of the reference clock signal is detected using a first internal clock signal, a parameter associated with jitter characteristics of the clock and data recovery circuit is adjusted according to the detected frequency band, and a second internal clock signal is output by adjusting a frequency of the first internal clock signal and when the CDR circuit receives the data packet, the data signal and a clock signal synchronized with the data signal are recovered from the data packet.