公开(公告)号：US12174683B2

公开(公告)日：2024-12-24

申请号：US17956195

申请日：2022-09-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhee Yoo ,  Jaehyun Kim ,  Jingyu Ahn ,  Wooil Kim ,  Manhwee Jo

IPC: G06F1/3234 ,  G11C7/22

Abstract: A system on chip (SoC) and an application processor are provided. The SoC includes a memory controller configured to control a memory; a plurality of function modules configured to access the memory through a memory interface; a system interconnect circuit configured to operate based on a first clock signal and connect the memory interface and the plurality of function modules; and a power controller configured to control the first clock signal to be periodically gated, and control the memory to operate in a lower-power mode during a period in which the first clock signal is gated.

公开(公告)号：US11093393B2

公开(公告)日：2021-08-17

申请号：US16289650

申请日：2019-02-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hien Le ,  Junhee Yoo ,  Vikas Kumar Sinha ,  Robert Bell ,  Matthew Derrick Garrett

IPC: G06F12/00 ,  G06F13/00 ,  G06F12/0815 ,  G06F12/0882 ,  G06F3/06 ,  G06F13/16

Abstract: A system and a method provide a memory-access technique that effectively parallelizes DRAM operations and coherency operations to reduce memory-access latency. The system may include a memory controller, an interconnect and a processor. The interconnect may be coupled to the memory controller. The processor may be coupled to the memory controller through a first path and a second path in which the first path is through the interconnect and the second path bypasses the interconnect. The processor may be configured to send substantially concurrently a memory access request to the memory controller via the first path and send a page activation request or a hint request to the memory controller via the second path so that the DRAM access operations appear to be masked, or hidden by the coherency operations.

公开(公告)号：US11417026B2

公开(公告)日：2022-08-16

申请号：US17034236

申请日：2020-09-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junhee Yoo

IPC: G06T9/00 ,  G06T7/11 ,  H03M7/30

Abstract: An operating method of an image processor includes dividing image data into a plurality of data blocks and compressing each of the plurality of data blocks. The operating method also includes determining a packing direction as a determined packing direction, in which a corresponding compressed data block of a plurality of compressed data blocks is to be stored, based on a data size of the corresponding compressed data block and a start address of a storage area where the corresponding compressed data block is to be stored among a plurality of storage areas of a memory. Each of the plurality of compressed data blocks is packed in a corresponding storage area among the plurality of storage areas of the memory based on the determined packing direction.

公开(公告)号：US20240248848A1

公开(公告)日：2024-07-25

申请号：US18505247

申请日：2023-11-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seulgi Seo ,  Junhee Yoo

IPC: G06F12/0864

CPC classification number: G06F12/0864 ,  G06F2212/6032

Abstract: An operating method of a set-associative cache includes selecting one way group from among a first way group and a second way group with different threshold voltages based on an operation state of the set-associative cache, increasing a number of ways to which power is supplied in the selected one way group, analyzing a change in an operation state of a system including the set-associative cache as the number of ways to which the power is supplied is increased, and determining whether to further increase the number of ways to which the power is supplied based on an analyzed change in the operation state of the system.