公开(公告)号：US20250132271A1

公开(公告)日：2025-04-24

申请号：US18912124

申请日：2024-10-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyojin Hwang ,  Junso Pak ,  Heeseok Lee

IPC: H01L23/64 ,  H01L23/498 ,  H01L25/16 ,  H05K1/11 ,  H05K1/18

Abstract: A semiconductor package includes a printed circuit board including a circuit pattern and a silicon capacitor connected to the circuit pattern, a semiconductor chip mounted on the printed circuit board, and an external connection terminal attached below the printed circuit board, wherein the silicon capacitor is a stacked structure of a plurality of substrate structures, each of the plurality of substrate structures includes a silicon substrate, a capacitor structure, a via electrode penetrating through the silicon substrate around the capacitor structure, an upper bump pad disposed on top of the via electrode, and a lower bump pad disposed below the via electrode, and, in the plurality of substrate structures, neighboring silicon substrates are bonded to each other through the upper bump pad and the lower bump pad facing each other.

公开(公告)号：US11908810B2

公开(公告)日：2024-02-20

申请号：US17489328

申请日：2021-09-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Heungkyu Kwon ,  Junso Pak ,  Heeseok Lee

IPC: H01L23/16 ,  H01L23/00

CPC classification number: H01L23/562 ,  H01L23/16

Abstract: A hybrid semiconductor device includes an interposer substrate, a semiconductor package mounted on the interposer substrate, a molding member on the package substrate covering at least a portion of the semiconductor chip and exposing an upper surface of the semiconductor chip, and a stiffener disposed on an upper surface of the interposer substrate substantially around the semiconductor package.

公开(公告)号：US11908758B2

公开(公告)日：2024-02-20

申请号：US17550284

申请日：2021-12-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Heungkyu Kwon ,  Junso Pak ,  Heeseok Lee

IPC: H01L23/16 ,  H01L23/053 ,  H01L23/31

CPC classification number: H01L23/16 ,  H01L23/053 ,  H01L23/31

Abstract: A semiconductor package includes; a dual stiffener including an upper stiffener and a lower stiffener, an upper package including an upper package substrate, a semiconductor chip centrally mounted on an upper surface of the upper package substrate, and the upper stiffener disposed along an outer edge of the upper package substrate, and a lower package substrate that centrally mounts the upper package and includes the lower stiffener disposed on an upper surface of the lower package substrate to surround the upper package substrate.

公开(公告)号：US12224260B2

公开(公告)日：2025-02-11

申请号：US17542667

申请日：2021-12-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Heejung Choi ,  Heeseok Lee ,  Junso Pak ,  Bongwee Yu

IPC: H01L23/00 ,  H01L23/498 ,  H01L25/10

Abstract: A semiconductor package including: a plurality of lower pads; an upper pad; a semiconductor chip including a chip pad and configured to transmit or receive a first signal through the chip pad; a first wiring structure connecting the chip pad to a first lower pad among the plurality of lower pads; and a second wiring structure connecting a second lower pad among the plurality of lower pads to the upper pad, wherein the first lower pad and the second lower pad are separated from each other by a minimum distance between the plurality of lower pads.

公开(公告)号：US12213256B2

公开(公告)日：2025-01-28

申请号：US17591734

申请日：2022-02-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junghwa Kim ,  Junso Pak ,  Heeseok Lee ,  Moonseob Jeong ,  Jisoo Hwang

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/48 ,  H01L23/538 ,  H05K1/02 ,  H05K1/18 ,  H01L25/065

Abstract: A semiconductor package including a circuit board including a first wiring region, a die mounting region surrounding the first wiring region, and a second wiring region surrounding the die mounting region; a plurality of wiring balls on the first wiring region and the second wiring region and spaced apart from one another, the plurality of wiring balls including a plurality of first wiring balls on the first wiring region and a plurality of second wiring balls on the second wiring region; a die on the die mounting region, the die including a plurality of unit chips spaced apart from one another, and a die-through region corresponding to the first wiring region and exposing the first wiring balls; and a plurality of die balls on the die and the die mounting region, the plurality of die balls being spaced apart from one another and electrically coupled to the circuit board.