公开(公告)号：US20240120927A1

公开(公告)日：2024-04-11

申请号：US18142939

申请日：2023-05-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jusung LEE ,  Wonsik YU ,  Youngwoo JO ,  Wooseok KIM

IPC: H03L7/091 ,  H03L7/089

CPC classification number: H03L7/091 ,  H03L7/089

Abstract: A phase-locked loop device and its operating method are provided. The phase-locked loop device includes a voltage controlled oscillator configured to generate an output clock signal, a divider configured to divide the output clock signal into first and second phase division signals having a constant phase difference, a sampling phase frequency detector configured to sample a sampling voltage based on the first phase division signal and output any one of the sampling voltage, a first supply voltage, and a second supply voltage based on the second phase division signal, a transconductance circuit configured to output a conversion current based on a hold voltage, and a loop filter configured to generate a voltage control signal based on the conversion current and output the voltage control signal to the voltage controlled oscillator.

公开(公告)号：US20230009620A1

公开(公告)日：2023-01-12

申请号：US17860519

申请日：2022-07-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jusung LEE ,  Wooseok Kim ,  Wonsik Yu ,  Chanyoung Jeong

IPC: H03L7/099 ,  H03L7/07 ,  H03L7/091 ,  H03L7/18

Abstract: A frequency-locked loop (FLL) logic circuit, including a validity signal generator configured to receive an external clock signal and determine whether a glitch occurs in the external clock signal; a clock divider configured to generate a reference frequency clock signal based on the external clock signal and a determination result of the validity signal generator; a synchronizer configured to synchronize a phase of an oscillator clock signal with a phase of the reference frequency clock signal; a clock counter configured to count a number of pulses of the oscillator clock signal during a reference time; and a code limiter configured to determine a range of a frequency selection value for calibrating an operating frequency of the oscillator clock signal based on the counted number of pulses.

公开(公告)号：US20220116155A1

公开(公告)日：2022-04-14

申请号：US17519818

申请日：2021-11-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongho KIM ,  Jongmin BAIK ,  Jusung LEE

IPC: H04L1/18 ,  H04W72/04 ,  H04B17/309

Abstract: Various embodiments of the disclosure relate to an apparatus and a method for managing a communication buffer of an electronic device in the electronic device. The electronic device includes: a wireless communication circuit, an application processor, and a communication processor operatively connected to the wireless communication circuit and the application processor and including a communication buffer, wherein the communication processor is configured to: identify a Radio Link Control (RLC) retransmission time, identify an uplink transmission rate, and configure a size of an area for storing data in the communication buffer based on the RLC retransmission time and the uplink transmission rate.